Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46798 )
Change subject: [WIP] soc/intel/broadwell: Clean up some headers ......................................................................
[WIP] soc/intel/broadwell: Clean up some headers
Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/cpu/bootblock.c M src/soc/intel/broadwell/cpu/cpu.c R src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/cpu/smmrelocate.c M src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/acpi.h D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c 16 files changed, 70 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46798/1
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..3927d3d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -17,10 +17,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c index ec3d588..042049d 100644 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -17,14 +17,13 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> +#include "haswell.h"
/* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/cpu/bootblock.c b/src/soc/intel/broadwell/cpu/bootblock.c index d6883c6..6460b69 100644 --- a/src/soc/intel/broadwell/cpu/bootblock.c +++ b/src/soc/intel/broadwell/cpu/bootblock.c @@ -6,8 +6,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <soc/rcba.h> -#include <soc/msr.h> #include <delay.h> +#include "haswell.h"
static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c index 72efa3d..036ca8c 100644 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ b/src/soc/intel/broadwell/cpu/cpu.c @@ -15,14 +15,13 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> +#include "haswell.h"
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/cpu/haswell.h similarity index 60% rename from src/soc/intel/broadwell/include/soc/msr.h rename to src/soc/intel/broadwell/cpu/haswell.h index 6a5f4dc..0f01457 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/cpu/haswell.h @@ -1,7 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _BROADWELL_MSR_H_ -#define _BROADWELL_MSR_H_ +#ifndef _CPU_BROADWELL_H_ +#define _CPU_BROADWELL_H_ + +#include <arch/cpu.h> +#include <stdint.h> + +/* CPU types */ +#define HASWELL_FAMILY_ULT 0x40650 +#define BROADWELL_FAMILY_ULT 0x306d0 + +/* Supported CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT 0x40651 +#define CPUID_HASWELL_HALO 0x40661 +#define CPUID_BROADWELL_C0 0x306d2 +#define CPUID_BROADWELL_D0 0x306d3 +#define CPUID_BROADWELL_E0 0x306d4 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100
#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -75,4 +96,39 @@ #define SMRR_SUPPORTED (1<<11) #define PRMRR_SUPPORTED (1<<12)
+/* Latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + +/* CPU identification */ +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + #endif diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c index c9f70a8..3434adf 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/soc/intel/broadwell/cpu/romstage.c @@ -3,9 +3,8 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/romstage.h> +#include "haswell.h"
void set_max_freq(void) { diff --git a/src/soc/intel/broadwell/cpu/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c index 3d4162a..df46f80 100644 --- a/src/soc/intel/broadwell/cpu/smmrelocate.c +++ b/src/soc/intel/broadwell/cpu/smmrelocate.c @@ -13,10 +13,9 @@ #include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include "haswell.h"
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/broadwell/cpu/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c index 4a8a343..fab1909 100644 --- a/src/soc/intel/broadwell/cpu/tsc_freq.c +++ b/src/soc/intel/broadwell/cpu/tsc_freq.c @@ -2,8 +2,7 @@
#include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include "haswell.h"
unsigned long tsc_freq_mhz(void) { diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index d42eebc..07b3ff8 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -15,7 +15,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/cpu.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -23,6 +22,7 @@ #include <security/vboot/vbnv.h> #include <soc/igd.h> #include <types.h> +#include "cpu/haswell.h"
#define GT_RETRY 1000 enum { diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 39d6cb4..97a37c7 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -6,12 +6,6 @@ #include <acpi/acpi.h> #include <soc/nvs.h>
-/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index bc5d2d7..0000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_CPU_H_ -#define _BROADWELL_CPU_H_ - -#include <arch/cpu.h> -#include <device/device.h> -#include <stdint.h> - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - -/* CPU identification */ -static inline u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -static inline u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -#endif diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index b9aeb38..af9a826 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -10,11 +10,11 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include "cpu/haswell.h"
u8 systemagent_revision(void) { diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 712bb46..9b20d89 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -17,10 +17,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index c98201e..99b3310 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -14,8 +14,8 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#include <soc/cpu.h> #include <delay.h> +#include "../cpu/haswell.h"
/* Low Power variant has 6 root ports. */ #define MAX_NUM_ROOT_PORTS 6 diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index baaf5ba..5036cd8 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -9,7 +9,8 @@ #include <device/pci_ops.h> #include <soc/ramstage.h> #include <soc/xhci.h> -#include <soc/cpu.h> +#include <arch/cpu.h> +#include "../cpu/haswell.h"
#ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 4ed84d7..3bc1622 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -7,11 +7,11 @@ #include <string.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> +#include "cpu/haswell.h"
static struct { u32 cpuid;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46798
to look at the new patch set (#4).
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
soc/intel/broadwell: Clean up headers
Stop having soc-namespaced headers.
Tested with BUILD_TIMELESS=1, Google Buddy remains identical.
Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/cpu/bootblock.c M src/soc/intel/broadwell/cpu/cpu.c A src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/cpu/smmrelocate.c M src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c R src/soc/intel/broadwell/haswell.h D src/soc/intel/broadwell/include/soc/acpi.h D src/soc/intel/broadwell/include/soc/cpu.h D src/soc/intel/broadwell/include/soc/device_nvs.h D src/soc/intel/broadwell/include/soc/igd.h D src/soc/intel/broadwell/include/soc/msr.h D src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/memmap.c R src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/adsp.c R src/soc/intel/broadwell/pch/adsp.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/ehci.c R src/soc/intel/broadwell/pch/ehci.h M src/soc/intel/broadwell/pch/elog.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/finalize.c M src/soc/intel/broadwell/pch/gpio.c R src/soc/intel/broadwell/pch/gpio.h M src/soc/intel/broadwell/pch/hda.c M src/soc/intel/broadwell/pch/iobp.c R src/soc/intel/broadwell/pch/iobp.h M src/soc/intel/broadwell/pch/lpc.c R src/soc/intel/broadwell/pch/lpc.h M src/soc/intel/broadwell/pch/me.c R src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/me_status.c R src/soc/intel/broadwell/pch/nvs.h M src/soc/intel/broadwell/pch/pch.c R src/soc/intel/broadwell/pch/pch.h M src/soc/intel/broadwell/pch/pcie.c R src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c R src/soc/intel/broadwell/pch/rcba.h M src/soc/intel/broadwell/pch/sata.c R src/soc/intel/broadwell/pch/sata.h M src/soc/intel/broadwell/pch/serialio.c R src/soc/intel/broadwell/pch/serialio.h M src/soc/intel/broadwell/pch/smbus.c R src/soc/intel/broadwell/pch/smbus.h M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c R src/soc/intel/broadwell/pch/spi.h M src/soc/intel/broadwell/pch/uart.c M src/soc/intel/broadwell/pch/xhci.c R src/soc/intel/broadwell/pch/xhci.h M src/soc/intel/broadwell/pei_data.c R src/soc/intel/broadwell/pei_data.h R src/soc/intel/broadwell/pei_wrapper.h M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/ramstage.c R src/soc/intel/broadwell/ramstage.h M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c R src/soc/intel/broadwell/romstage.h 127 files changed, 528 insertions(+), 581 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46798/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46798
to look at the new patch set (#6).
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
soc/intel/broadwell: Clean up headers
Stop having soc-namespaced headers.
Tested with BUILD_TIMELESS=1, Google Buddy remains identical.
Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/cpu/bootblock.c M src/soc/intel/broadwell/cpu/cpu.c A src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/cpu/smmrelocate.c M src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c R src/soc/intel/broadwell/haswell.h D src/soc/intel/broadwell/include/soc/acpi.h D src/soc/intel/broadwell/include/soc/cpu.h D src/soc/intel/broadwell/include/soc/device_nvs.h D src/soc/intel/broadwell/include/soc/igd.h D src/soc/intel/broadwell/include/soc/msr.h D src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/memmap.c R src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/adsp.c R src/soc/intel/broadwell/pch/adsp.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/ehci.c R src/soc/intel/broadwell/pch/ehci.h M src/soc/intel/broadwell/pch/elog.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/finalize.c M src/soc/intel/broadwell/pch/gpio.c R src/soc/intel/broadwell/pch/gpio.h M src/soc/intel/broadwell/pch/hda.c M src/soc/intel/broadwell/pch/iobp.c R src/soc/intel/broadwell/pch/iobp.h M src/soc/intel/broadwell/pch/lpc.c R src/soc/intel/broadwell/pch/lpc.h M src/soc/intel/broadwell/pch/me.c R src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/me_status.c R src/soc/intel/broadwell/pch/nvs.h M src/soc/intel/broadwell/pch/pch.c R src/soc/intel/broadwell/pch/pch.h M src/soc/intel/broadwell/pch/pcie.c R src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c R src/soc/intel/broadwell/pch/rcba.h M src/soc/intel/broadwell/pch/sata.c R src/soc/intel/broadwell/pch/sata.h M src/soc/intel/broadwell/pch/serialio.c R src/soc/intel/broadwell/pch/serialio.h M src/soc/intel/broadwell/pch/smbus.c R src/soc/intel/broadwell/pch/smbus.h M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c R src/soc/intel/broadwell/pch/spi.h M src/soc/intel/broadwell/pch/uart.c M src/soc/intel/broadwell/pch/xhci.c R src/soc/intel/broadwell/pch/xhci.h M src/soc/intel/broadwell/pei_data.c R src/soc/intel/broadwell/pei_data.h R src/soc/intel/broadwell/pei_wrapper.h M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/ramstage.c R src/soc/intel/broadwell/ramstage.h M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c R src/soc/intel/broadwell/romstage.h 127 files changed, 530 insertions(+), 582 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46798/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46798
to look at the new patch set (#10).
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
soc/intel/broadwell: Clean up headers
Stop having soc-namespaced headers.
Tested with BUILD_TIMELESS=1, Google Buddy remains identical.
Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/pei_data.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c M src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/cpu/bootblock.c M src/soc/intel/broadwell/cpu/cpu.c A src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/cpu/smmrelocate.c M src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c R src/soc/intel/broadwell/haswell.h D src/soc/intel/broadwell/include/soc/acpi.h D src/soc/intel/broadwell/include/soc/cpu.h D src/soc/intel/broadwell/include/soc/device_nvs.h D src/soc/intel/broadwell/include/soc/igd.h D src/soc/intel/broadwell/include/soc/msr.h D src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/memmap.c R src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/adsp.c R src/soc/intel/broadwell/pch/adsp.h M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/ehci.c R src/soc/intel/broadwell/pch/ehci.h M src/soc/intel/broadwell/pch/elog.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/finalize.c M src/soc/intel/broadwell/pch/gpio.c R src/soc/intel/broadwell/pch/gpio.h M src/soc/intel/broadwell/pch/hda.c M src/soc/intel/broadwell/pch/iobp.c R src/soc/intel/broadwell/pch/iobp.h M src/soc/intel/broadwell/pch/lpc.c R src/soc/intel/broadwell/pch/lpc.h M src/soc/intel/broadwell/pch/me.c R src/soc/intel/broadwell/pch/me.h M src/soc/intel/broadwell/pch/me_status.c R src/soc/intel/broadwell/pch/nvs.h M src/soc/intel/broadwell/pch/pch.c R src/soc/intel/broadwell/pch/pch.h M src/soc/intel/broadwell/pch/pcie.c R src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c R src/soc/intel/broadwell/pch/rcba.h M src/soc/intel/broadwell/pch/sata.c R src/soc/intel/broadwell/pch/sata.h M src/soc/intel/broadwell/pch/serialio.c R src/soc/intel/broadwell/pch/serialio.h M src/soc/intel/broadwell/pch/smbus.c R src/soc/intel/broadwell/pch/smbus.h M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c R src/soc/intel/broadwell/pch/spi.h M src/soc/intel/broadwell/pch/uart.c M src/soc/intel/broadwell/pch/xhci.c R src/soc/intel/broadwell/pch/xhci.h M src/soc/intel/broadwell/pei_data.c R src/soc/intel/broadwell/pei_data.h R src/soc/intel/broadwell/pei_wrapper.h M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/ramstage.c R src/soc/intel/broadwell/ramstage.h M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c R src/soc/intel/broadwell/romstage.h 127 files changed, 530 insertions(+), 582 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46798/10
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46798 )
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46798/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46798/10//COMMIT_MSG@11 PS10, Line 11: Tested with BUILD_TIMELESS=1, Google Buddy remains identical. Please test all adapted variants.
https://review.coreboot.org/c/coreboot/+/46798/10/src/soc/intel/broadwell/me... File src/soc/intel/broadwell/memmap.h:
PS10: It's not all mem, is it?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46798 )
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46798/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46798/10//COMMIT_MSG@11 PS10, Line 11: Tested with BUILD_TIMELESS=1, Google Buddy remains identical.
Please test all adapted variants.
That is, test all Broadwell boards. Will do (rather, make abuild do most of the job for me).
https://review.coreboot.org/c/coreboot/+/46798/10/src/soc/intel/broadwell/me... File src/soc/intel/broadwell/memmap.h:
PS10:
It's not all mem, is it?
it's not all io, is it?
In any case, I plan on getting rid of at least the SMBus I/O BAR definitions in future patches. I should mention it in the commit message.
Angel Pons has removed Nico Huber from this change. ( https://review.coreboot.org/c/coreboot/+/46798 )
Change subject: soc/intel/broadwell: Clean up headers ......................................................................
Removed reviewer Nico Huber.
-
Angel Pons (Code Review) -
Nico Huber (Code Review)