Attention is currently required from: Arthur Heymans, Nico Huber, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )
Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/intel/socket_p/Kconfig:
https://review.coreboot.org/c/coreboot/+/52942/comment/e2d7ec11_e5cf1912
PS1, Line 16: default 0x10000
DCACHE_RAM_SIZE would be the data region. for code, we use the size of the stage. […]
I had swiftgeek test CB:54002 on X200
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