[XS] Change in coreboot[main]: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79334?usp=email )

Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
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mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1

The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.

On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.

This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.

Test=Boot into Linux and make sure a write access into the EEPROM is
possible.

Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) 
Reviewed-by: Jan Samek 
---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jan Samek: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index 28fca2d..d386d75 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -38,4 +38,8 @@

/* Enable Row-Hammer prevention */
    memupd->FspmConfig.RhPrevention = 1;
+	if (CONFIG(BOARD_SIEMENS_MC_EHL1)) {
+		/* Allow writes to EEPROM addresses 0x50..0x57. */
+		memupd->FspmConfig.SmbusSpdWriteDisable = 0;
+	}
 }