[S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS

[Jérémy Compostella (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Kapil Porwal, Pranava Y N, Subrata Banik.

Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email )

Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS
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Patch Set 4:

(2 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/86002/comment/1f0a4fb8_0f046c0c?usp... :
PS4, Line 19: 	select FSP_DEBUG_LOG_LEVEL_USING_CBFS if MAINBOARD_HAS_CHROMEOS
Why does it depend on MAINBOARD_HAS_CHROMEOS?

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/86002/comment/64f2be2c_7270be59?usp... :
PS4, Line 314: 	if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS) && is_enabled) {
It looks quite a cumbersome construction to me, what adding and using the following helper function:
```
static enum fsp_log_level fsp_get_log_level(bool is_enabled)
{
    if (!is_enabled)
    	return FSP_LOG_LEVEL_DISABLE;

if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS))
    	return get_fsp_mrc_debug_log_level();

return fsp_map_console_log_level();
}
```