[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email )

Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
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mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8

Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.

BUG=b:366383364
TEST=Tested on Awasuki with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2

Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418
Signed-off-by: Hualin Wei 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Weimin Wu 
Reviewed-by: Karthik Ramasubramanian 
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Weimin Wu: Looks good to me, but someone else must approve
  Eric Lai: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
index cc7eba83..e0abe19 100644
--- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
@@ -1,4 +1,7 @@
 chip soc/intel/jasperlake
+	# PCIe RP LTR configuration
+	register "PcieRpLtrEnable[7]" = "1"
+
    # USB Port Configuration
    register "usb2_ports[1]" = "USB2_PORT_EMPTY"
    register "usb2_ports[3]" = "USB2_PORT_EMPTY"