[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85635?usp=email )

Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
......................................................................

drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver

Define the generic cbmem_top_chipset() in the driver code, which will
invoke a SoC-specific vendorcode openSIL call to retrieve the low
usable DRAM address.

Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359
Signed-off-by: Nicolas Kochlowski 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/drivers/amd/opensil/Makefile.mk
A src/drivers/amd/opensil/romstage.c
M src/vendorcode/amd/opensil/genoa_poc/romstage.c
M src/vendorcode/amd/opensil/opensil.h
M src/vendorcode/amd/opensil/stub/romstage.c
5 files changed, 38 insertions(+), 24 deletions(-)

Approvals:
  Felix Held: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk
index 82e025b..9837718 100644
--- a/src/drivers/amd/opensil/Makefile.mk
+++ b/src/drivers/amd/opensil/Makefile.mk
@@ -4,6 +4,8 @@

subdirs-y += mpio

+romstage-y += romstage.c
+
 ramstage-y += acpi.c
 ramstage-y += ramstage.c

diff --git a/src/drivers/amd/opensil/romstage.c b/src/drivers/amd/opensil/romstage.c
new file mode 100644
index 0000000..b9ef239
--- /dev/null
+++ b/src/drivers/amd/opensil/romstage.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/mtrr.h>
+#include <vendorcode/amd/opensil/opensil.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	printk(BIOS_DEBUG, "TOM1: 0x%x\n", get_top_of_mem_below_4gb());
+	uintptr_t top_mem = opensil_get_low_usable_dram_address();
+
+	/* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size to
+	   account for potentially ill aligned TOP_MEM. */
+	if (CONFIG_SMM_TSEG_SIZE) {
+		top_mem -= CONFIG_SMM_TSEG_SIZE;
+		top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
+	}
+
+	return top_mem;
+}
diff --git a/src/vendorcode/amd/opensil/genoa_poc/romstage.c b/src/vendorcode/amd/opensil/genoa_poc/romstage.c
index e55ed1b..5b871f6 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/romstage.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/romstage.c
@@ -1,23 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <cbmem.h>
 #include <console/console.h>
 #include "opensil_console.h"
 #include <xSIM-api.h>
 #include <xPRF-api.h>

-uintptr_t cbmem_top_chipset(void)
+#include "../opensil.h"
+
+uintptr_t opensil_get_low_usable_dram_address(void)
 {
    SilDebugSetup(HostDebugService);
-	uintptr_t top_mem = xPrfGetLowUsableDramAddress(0);
-	printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", top_mem);
+	uintptr_t low_usable_dram_addr = xPrfGetLowUsableDramAddress(0);
+	printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", low_usable_dram_addr);

-	/* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so
-	   account for potentially ill aligned TOP_MEM. */
-	if (CONFIG_SMM_TSEG_SIZE) {
-		top_mem -= CONFIG_SMM_TSEG_SIZE;
-		top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
-	}
-
-	return top_mem;
+	return low_usable_dram_addr;
 }
diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h
index cd71dfc..c84a180 100644
--- a/src/vendorcode/amd/opensil/opensil.h
+++ b/src/vendorcode/amd/opensil/opensil.h
@@ -5,6 +5,7 @@

#include <acpi/acpi.h>
 #include <device/device.h>
+#include <types.h>

void SIL_STATUS_report(const char *function, const int status);
 // Add the memory map to dev, starting at index idx, returns last use idx
@@ -13,6 +14,8 @@
 void opensil_fill_fadt(acpi_fadt_t *fadt);
 unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp);

+uintptr_t opensil_get_low_usable_dram_address(void);
+
 void setup_opensil(void);
 void opensil_xSIM_timepoint_1(void);
 void opensil_xSIM_timepoint_2(void);
diff --git a/src/vendorcode/amd/opensil/stub/romstage.c b/src/vendorcode/amd/opensil/stub/romstage.c
index 36dff95..989843f 100644
--- a/src/vendorcode/amd/opensil/stub/romstage.c
+++ b/src/vendorcode/amd/opensil/stub/romstage.c
@@ -1,23 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <cbmem.h>
 #include <console/console.h>
 #include <inttypes.h>

-uintptr_t cbmem_top_chipset(void)
+#include "../opensil.h"
+
+uintptr_t opensil_get_low_usable_dram_address(void)
 {
    /* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to
       call, we just use 0xc0000000 here which should be a usable value in most cases */
-	uintptr_t top_mem = 0xc0000000;
+	uintptr_t low_usable_dram_addr = 0xc0000000;

-	printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem);
+	printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, low_usable_dram_addr);

-	/* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so
-	   account for potentially ill aligned TOP_MEM. */
-	if (CONFIG_SMM_TSEG_SIZE) {
-		top_mem -= CONFIG_SMM_TSEG_SIZE;
-		top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE);
-	}
-
-	return top_mem;
+	return low_usable_dram_addr;
 }