[M] Change in coreboot[master]: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70049 )

Change subject: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()
......................................................................

[WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()

Renames {read,write}_pmbaseX to pm_{read,write}X.

Inlining allows for static, compile-time assertions and
possibility to easily add register tracing for debugging.

Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2
Signed-off-by: Kyösti Mälkki 
---
M src/southbridge/intel/common/pmbase.c
M src/southbridge/intel/common/pmbase.h
2 files changed, 119 insertions(+), 52 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/70049/1

diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
index ba7111b..46b8518 100644
--- a/src/southbridge/intel/common/pmbase.c
+++ b/src/southbridge/intel/common/pmbase.c
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
-#include <arch/io.h>
-#include <assert.h>
 #include <bootmode.h>
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
@@ -11,8 +9,6 @@
 #include "pmbase.h"
 #include "pmutil.h"

-#define PMSIZE		0x80
-
 #if !CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) && !CONFIG(SOC_INTEL_BAYTRAIL) && \
     !CONFIG(SOC_INTEL_BRASWELL)

@@ -46,48 +42,6 @@
 }
 #endif

-void write_pmbase32(const u8 addr, const u32 val)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u32)));
-
-	outl(val, get_pmbase() + addr);
-}
-
-void write_pmbase16(const u8 addr, const u16 val)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u16)));
-
-	outw(val, get_pmbase() + addr);
-}
-
-void write_pmbase8(const u8 addr, const u8 val)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u8)));
-
-	outb(val, get_pmbase() + addr);
-}
-
-u32 read_pmbase32(const u8 addr)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u32)));
-
-	return inl(get_pmbase() + addr);
-}
-
-u16 read_pmbase16(const u8 addr)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u16)));
-
-	return inw(get_pmbase() + addr);
-}
-
-u8 read_pmbase8(const u8 addr)
-{
-	ASSERT(addr <= (PMSIZE - sizeof(u8)));
-
-	return inb(get_pmbase() + addr);
-}
-
 int acpi_get_sleep_type(void)
 {
    return acpi_sleep_from_pm1(read_pmbase32(PM1_CNT));
diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h
index 451c3f5..171ce4a 100644
--- a/src/southbridge/intel/common/pmbase.h
+++ b/src/southbridge/intel/common/pmbase.h
@@ -3,8 +3,24 @@
 #ifndef __INTEL_COMMON_PMBASE__
 #define __INTEL_COMMON_PMBASE__

+#include <arch/io_bitops.h>
+#include <assert.h>
 #include <stdint.h>

+#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) || CONFIG(SOC_INTEL_BROADWELL)
+/* Wider GPIO space, TCO range is in the middle 0x60..0x80. */
+#define PMSIZE 0x100
+#elif CONFIG(TCO_SPACE_NOT_YET_SPLIT)
+/* Must let TCO registers 0x60..0x80 through. */
+#define PMSIZE 0x80
+#elif CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)
+/* TCO registers 0x60..0x80 moved, these are now GPEs. */
+#define PMSIZE 0x80
+#else
+/* Only allow true PM registers, the ones below TCO. */
+#define PMSIZE 0x60
+#endif
+
 /* FIXME: ENV_SMM must reload base on each entry to SMI ? */
 #define HAVE_DYNAMIC_ACPI_BASE_ADDRESS ENV_SMM

@@ -45,12 +61,94 @@
 }
 #endif

-void write_pmbase32(const u8 addr, const u32 val);
-void write_pmbase16(const u8 addr, const u16 val);
-void write_pmbase8(const u8 addr, const u8 val);
+static __always_inline void pm_write32(const u16 addr, const u32 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+	io_write32(get_pmbase() + addr, val);
+}

-u32 read_pmbase32(const u8 addr);
-u16 read_pmbase16(const u8 addr);
-u8 read_pmbase8(const u8 addr);
+static __always_inline void pm_write16(const u16 addr, const u16 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+	io_write16(get_pmbase() + addr, val);
+}
+
+static __always_inline void pm_write8(const u16 addr, const u8 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+	io_write8(get_pmbase() + addr, val);
+}
+
+static __always_inline u32 pm_read32(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+	return io_read32(get_pmbase() + addr);
+}
+
+static __always_inline u16 pm_read16(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+	return io_read16(get_pmbase() + addr);
+}
+
+static __always_inline u8 pm_read8(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+	return io_read8(get_pmbase() + addr);
+}
+
+static __always_inline u32 pm_rwc32(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+	return io_rwc32(get_pmbase() + addr);
+}
+
+static __always_inline u16 pm_rwc16(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+	return io_rwc16(get_pmbase() + addr);
+}
+
+static __always_inline u8 pm_rwc8(const u16 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+	return io_rwc8(get_pmbase() + addr);
+}
+
+static __always_inline void pm_clrsetbits32(const u16 addr, const u32 clr, const u32 set)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+	io_clrsetbits32(get_pmbase() + addr, clr, set);
+}
+
+static __always_inline void pm_clrsetbits16(const u16 addr, const u16 clr, const u16 set)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+	io_clrsetbits16(get_pmbase() + addr, clr, set);
+}
+
+static __always_inline void pm_clrsetbits8(const u16 addr, const u8 clr, const u8 set)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+	io_clrsetbits8(get_pmbase() + addr, clr, set);
+}
+
+#define pm_setbits32(addr, set) pm_clrsetbits32(addr, 0, set)
+#define pm_setbits16(addr, set) pm_clrsetbits16(addr, 0, set)
+#define pm_setbits8(addr, set) pm_clrsetbits8(addr, 0, set)
+
+#define pm_clrbits32(addr, clr) pm_clrsetbits32(addr, clr, 0)
+#define pm_clrbits16(addr, clr) pm_clrsetbits16(addr, clr, 0)
+#define pm_clrbits8(addr, clr) pm_clrsetbits8(addr, clr, 0)
+
+
+
+/* Transitional macros */
+#define write_pmbase32 pm_write32
+#define write_pmbase16 pm_write16
+#define write_pmbase8 pm_write8
+#define read_pmbase32 pm_read32
+#define read_pmbase16 pm_read16
+#define read_pmbase8 pm_read8

#endif