[XS] Change in coreboot[main]: tree: Use eist_enable as bool for newly merged files

[Elyes Haouas (Code Review)]

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84156?usp=email )

Change subject: tree: Use eist_enable as bool for newly merged files
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tree: Use eist_enable as bool for newly merged files

Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6
Signed-off-by: Elyes Haouas 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156
Reviewed-by: Sean Rhodes 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/protectli/vault_adl_p/devicetree.cb
M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
M src/mainboard/system76/mtl/devicetree.cb
3 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Sean Rhodes: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb
index f11dc6a..0089a5f 100644
--- a/src/mainboard/protectli/vault_adl_p/devicetree.cb
+++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/alderlake
    # FSP configuration

-	register "eist_enable" = "1"
+	register "eist_enable" = "true"

# Sagv Configuration
    register "sagv" = "SaGv_Enabled"
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index 145dbc2..5a6424e 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -13,7 +13,7 @@
    register "sagv"				= "SaGv_Enabled"

# FSP Silicon
-	register "eist_enable"			= "1"
+	register "eist_enable"			= "true"
    register "cnvi_bt_core"			= "true"
    register "cnvi_bt_audio_offload"	= "true"

diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb
index 9a4cfb4..0bd6721 100644
--- a/src/mainboard/system76/mtl/devicetree.cb
+++ b/src/mainboard/system76/mtl/devicetree.cb
@@ -11,7 +11,7 @@
    }"

# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"

# Thermal
    register "tcc_offset" = "8"