Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28791 )

Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip_... 
File src/soc/intel/skylake/chip_fsp20.c:

https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip_... 
PS3, Line 177: 	fsp_silicon_init(romstage_handoff_is_resume());
This includes calling back to the soc and then the mainboard code
(mainboard_silicon_init_params()) where many boards configure the
pads which includes configuring IRQ polarities. So it may supersede
the config that was backed up above.

This shows that we have way too many hooks around. It seems, nobody
can keep track when what is called. I'm thinking about dropping
mainboard_silicon_init_params(), it seems only useful for downstream
solutions (i.e. if the soc/ code doesn't fill the params properly,
that should be fixed instead).

This would leave us with the question when to do the pad configu-
ration? Any suggestions? Some boards do it in the mainboard's
chip->init(), which should work for this case, but I wonder if
we shouldn't just make it a rule to always do it early, e.g.
part of the romstage soc control flow?