[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 9:

(1 comment)

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/1d7d3fb5_8363be47?usp... :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> Subrata, we are still switching in between using GPE0 and GPE1 for further validation until we verify all GPE1 bits are working at this time. here, we will still need this flag here, and also in ASL files and code for SSDT.

i don't agree that you need a CPP here. what you are trying to protect here in a header file by adding CPP guard ? these are registers definition for PTL and where we are selecting `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` or not, these GPE1 definitions are here to stay. Hence, you can drop the line #133 and line #137. Rest looks good to me