Patch set updated for coreboot: e4751af Replace hlt() loops with halt()

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7606

-gerrit

commit e4751afc96a1229b79dc5aea137e9429b4bf67a8
Author: Patrick Georgi 
Date:   Fri Nov 28 22:35:36 2014 +0100

Replace hlt() loops with halt()

Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
    Signed-off-by: Patrick Georgi 
    Signed-off-by: Patrick Georgi 
---
 src/console/die.c                                  |  6 ++----
 src/cpu/intel/haswell/romstage.c                   |  5 ++---
 src/cpu/x86/lapic/lapic_cpu_init.c                 |  6 ++----
 src/include/cpu/x86/lapic.h                        |  6 ++----
 src/mainboard/asus/a8v-e_deluxe/romstage.c         |  6 ++----
 src/mainboard/asus/a8v-e_se/romstage.c             |  6 ++----
 src/mainboard/asus/k8v-x/romstage.c                |  6 ++----
 src/mainboard/asus/m2v-mx_se/romstage.c            |  6 ++----
 src/mainboard/asus/m2v/romstage.c                  |  6 ++----
 src/mainboard/dmp/vortex86ex/romstage.c            |  4 ++--
 src/mainboard/intel/cougar_canyon2/romstage.c      |  5 ++---
 src/northbridge/intel/haswell/raminit.c            |  6 ++----
 src/northbridge/intel/sandybridge/raminit_native.c | 10 ++++------
 src/soc/intel/baytrail/romstage/raminit.c          |  4 ++--
 src/soc/intel/broadwell/reset.c                    |  6 ++----
 src/southbridge/intel/lynxpoint/early_me.c         |  6 ++----
 16 files changed, 34 insertions(+), 60 deletions(-)

diff --git a/src/console/die.c b/src/console/die.c
index 395ab75..e6e968a 100644
--- a/src/console/die.c
+++ b/src/console/die.c
@@ -20,8 +20,8 @@
  */

#include <arch/io.h>
-#include <arch/hlt.h>
 #include <console/console.h>
+#include <halt.h>

#ifndef __ROMCC__
 #define NORETURN __attribute__((noreturn))
@@ -33,7 +33,5 @@
 void NORETURN die(const char *msg)
 {
    print_emerg(msg);
-	do {
-		hlt();
-	} while(1);
+	halt();
 }
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index edb2fdf..bd2513f 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -25,6 +25,7 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <halt.h>
 #include <lib.h>
 #include <timestamp.h>
 #include <arch/io.h>
@@ -49,9 +50,7 @@
 static inline void reset_system(void)
 {
    hard_reset();
-	while (1) {
-		hlt();
-	}
+	halt();
 }

/* The cache-as-ram assembly file calls romstage_main() after setting up
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 018924f..61b6bd7 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -23,10 +23,10 @@
 #include <cpu/x86/cr.h>
 #include <cpu/x86/lapic.h>
 #include <delay.h>
+#include <halt.h>
 #include <lib.h>
 #include <string.h>
 #include <console/console.h>
-#include <arch/hlt.h>
 #include <device/device.h>
 #include <device/path.h>
 #include <smp/atomic.h>
@@ -396,9 +396,7 @@ void stop_this_cpu(void)
 #endif
    }

-	while(1) {
-		hlt();
-	}
+	halt();
 }
 #endif

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 3d5046e..16bc42d 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -3,7 +3,7 @@

#include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
-#include <arch/hlt.h>
+#include <halt.h>
 #include <smp/node.h>

/* See if I need to initialize the local apic */
@@ -59,9 +59,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
 static inline __attribute__((always_inline)) void stop_this_cpu(void)
 {
    /* Called by an AP when it is ready to halt and wait for a new task */
-	for(;;) {
-		hlt();
-	}
+	halt();
 }
 #else
 void stop_this_cpu(void);
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index c137b14..0d55e53 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -71,10 +72,7 @@ void soft_reset(void)
    tmp |= 0x01;
    pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }

#include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 5c78ab1..3ed2491 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -71,10 +72,7 @@ void soft_reset(void)
    tmp |= 0x01;
    pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }

#include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 15b8682..dab3193 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -69,10 +70,7 @@ void soft_reset(void)
    tmp |= 0x01;
    pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }

#include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index adcdfc7..42b03c8 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -99,10 +100,7 @@ void soft_reset(void)
    /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
    pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }

unsigned int get_sbdn(unsigned bus)
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 30ba468..f776351 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -83,10 +84,7 @@ void soft_reset(void)
    /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
    pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);

-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }

unsigned int get_sbdn(unsigned bus)
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
index e7933d5..d43df8d 100644
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -23,6 +23,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
+#include <halt.h>
 #include "drivers/pc80/i8254.c"
 #include "northbridge/dmp/vortex86ex/northbridge.h"
 #include "southbridge/dmp/vortex86ex/southbridge.h"
@@ -309,8 +310,7 @@ static void main(unsigned long bist)
    if (dmp_id != DMP_CPUID_EX) {
    	/* Not DMP Vortex86EX CPU. */
    	post_code(POST_DMP_ID_ERR);
-		while (1)
-			hlt();
+		halt();
    }
    disable_watchdog();
    set_ex_powerdown_control();
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 9ac70ef..c90ece2 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -31,6 +31,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <halt.h>
 #include <reset.h>
 #include "superio/smsc/sio1007/chip.h"
 #include <fsp_util.h>
@@ -49,9 +50,7 @@
 static inline void reset_system(void)
 {
    hard_reset();
-	while (1) {
-		hlt();
-	}
+	halt();
 }

static void pch_enable_lpc(void)
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 1577e68..197dc0f 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -20,11 +20,11 @@
 #include <console/console.h>
 #include <bootmode.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
+#include <halt.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
@@ -155,9 +155,7 @@ void sdram_initialize(struct pei_data *pei_data)
    	printk(BIOS_DEBUG, "Giving up in sdram_initialize: "
    	       "No MRC data\n");
    	outb(0x6, 0xcf9);
-		while(1) {
-			hlt();
-		}
+		halt();
    }

/* Pass console handler in pei_data */
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 9de39c6..de6dac7 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -22,11 +22,11 @@
 #include <console/usb.h>
 #include <bootmode.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
+#include <halt.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
@@ -3728,7 +3728,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
    	/* Need reset.  */
    	outb(0x6, 0xcf9);

-		hlt();
+		halt();
    }

ramctr_timing ctrl;
@@ -3751,9 +3751,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
    	if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) {
    		/* Failed S3 resume, reset to come up cleanly */
    		outb(0x6, 0xcf9);
-			while (1) {
-				hlt();
-			}
+			halt();
    	}
    	memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl));
    }
@@ -3887,6 +3885,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
    if (s3resume && !cbmem_was_inited) {
    	/* Failed S3 resume, reset to come up cleanly */
    	outb(0x6, 0xcf9);
-		hlt();
+		halt();
    }
 }
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 72d8e51..a51853a 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -18,13 +18,13 @@
  */

#include <stddef.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <bootmode.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <device/pci_def.h>
+#include <halt.h>
 #include <baytrail/gpio.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <baytrail/iomap.h>
@@ -38,7 +38,7 @@
 static void reset_system(void)
 {
    warm_reset();
-	while(1) { hlt(); }
+	halt();
 }

static void enable_smbus(void)
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index ffd15e7..5117b29 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */

-#include <arch/hlt.h>
 #include <arch/io.h>
+#include <halt.h>
 #include <reset.h>
 #include <broadwell/reset.h>

@@ -45,7 +45,5 @@ void hard_reset(void)
 void reset_system(void)
 {
    hard_reset();
-	while (1) {
-		hlt();
-	}
+	halt();
 }
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 6b61eac..b57ca73 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -19,11 +19,11 @@
  * MA 02110-1301 USA
  */

-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_ids.h>
+#include <halt.h>
 #include <string.h>
 #include "me.h"
 #include "pch.h"
@@ -199,9 +199,7 @@ int intel_early_me_init_done(u8 status)
    /* Perform the requested reset */
    if (reset) {
    	outb(reset, 0xcf9);
-		while (1) {
-			hlt();
-		}
+		halt();
    }
    return -1;
 }