Change in coreboot[master]: cpu/amd/fam10: Link fidvid.c

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20973

Change subject: cpu/amd/fam10: Link fidvid.c
......................................................................

cpu/amd/fam10: Link fidvid.c

Change-Id: I724fa6c3ba0cc4fdfb11cc28fd54611c5959f2fb
Signed-off-by: Arthur Heymans 
---
M src/cpu/amd/family_10h-family_15h/Makefile.inc
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/init_cpus.h
4 files changed, 24 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/20973/1

diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index c540320..aa9b4d0 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -1,5 +1,6 @@
 romstage-y += ../../x86/mtrr/earlymtrr.c

+romstage-y += fidvid.c
 romstage-y += init_cpus.c

ramstage-y += model_10xxx_init.c
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index e4bb9a3..af3a674 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -89,8 +89,16 @@

*/

+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
 #include <inttypes.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/ht_wrapper.h>
+#include <cpu/amd/multicore.h>
+
+#include "init_cpus.h"

static inline void print_debug_fv(const char *str, u32 val)
 {
@@ -859,7 +867,7 @@

}

-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
+void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
 {
    u32 send;

diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index f5a949c..be4f8d4 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -138,7 +138,7 @@
 //core range = 1 : core 0 only
 //core range = 2 : cores other than core0

-static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
+void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
    		process_ap_t process_ap, void *gp)
 {
    // here assume the OS don't change our apicid
@@ -198,7 +198,7 @@
    }
 }

-static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 {
    int timeout;
    u32 status;
@@ -226,10 +226,6 @@
    }
    return result;
 }
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
-#endif

static inline __attribute__((always_inline))
 void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
@@ -764,7 +760,7 @@
    }
 }

-static u32 get_platform_type(void)
+u32 get_platform_type(void)
 {
    u32 ret = 0;

@@ -825,7 +821,7 @@
  *
  * Returns the offset of the link register.
  */
-static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
+BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
 {
    u32 reg;
    u32 val;
@@ -865,7 +861,7 @@
  *
  * Returns the link characteristic mask.
  */
-static u32 AMD_checkLinkType(u8 node, u8 regoff)
+u32 AMD_checkLinkType(u8 node, u8 regoff)
 {
    uint32_t val;
    uint32_t val2;
@@ -1878,7 +1874,3 @@
    }
 #endif
 }
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-# include "fidvid.c"
-#endif
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h
index d4bff0b..8ca9c8b 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.h
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h
@@ -25,6 +25,7 @@
 #include <cpu/amd/multicore.h>
 #include <reset.h>
 #include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdht/porting.h>
 #include "defaults.h"

#define NODE_HT(x) NODE_PCI(x,0)
@@ -45,6 +46,13 @@
 uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
 void start_other_cores(uint32_t bsp_apicid);
 u32 get_core_num_in_bsp(u32 nodeid);
+void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
+		process_ap_t process_ap, void *gp);
+u32 get_platform_type(void);
+BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset);
+u32 AMD_checkLinkType(u8 node, u8 regoff);
+int lapic_remote_read(int apicid, int reg, u32 *pvalue);
+

void update_microcode(u32 cpu_deviceid);

@@ -52,5 +60,6 @@
 void init_fidvid_stage2(u32 apicid, u32 nodeid);
 void prep_fid_change(void);
 int init_fidvid_bsp(u32 bsp_apicid, u32 nodes);
+void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);

#endif