Change in coreboot[master]: soc/intel/tigerlake: Configure ClkReq according to mainboard design

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38285 )

Change subject: soc/intel/tigerlake: Configure ClkReq according to mainboard design
......................................................................

soc/intel/tigerlake: Configure ClkReq according to mainboard design

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe

Signed-off-by: Wonkyu Kim 
Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
1 file changed, 4 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 388ac42..a4533c9 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -60,12 +60,15 @@
    		m_cfg->PcieClkSrcUsage[i] = 0xff;
    }

+	memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+		sizeof(config->PcieClkSrcClkReq));
+
    m_cfg->PrmrrSize = config->PrmrrSize;
    m_cfg->EnableC6Dram = config->enable_c6dram;
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;

-	/* UART Debug Log*/
+	/* UART Debug Log */
    m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
    		DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
    m_cfg->PcdIsaSerialUartBase = 0x0;