Change in coreboot[master]: soc/xeon_sp: add configs to use common/gpio diver

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39428 )

Change subject: soc/xeon_sp: add configs to use common/gpio diver
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soc/xeon_sp: add configs to use common/gpio diver

Allow the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.

This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1].

[1] https://review.coreboot.org/c/coreboot/+/39425

Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 468cb44..b10c7be 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -61,6 +61,10 @@
    select SOC_INTEL_COMMON_BLOCK_RTC
    select SOC_INTEL_COMMON_BLOCK_SPI
    select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
+	select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
+	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
    select SOC_INTEL_COMMON_BLOCK_PCR
    select TSC_MONOTONIC_TIMER
    select UDELAY_TSC