[XS] Change in coreboot[main]: soc/amd/common,genoa_poc/domain: rework check for 1st domain

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79996?usp=email )

Change subject: soc/amd/common,genoa_poc/domain: rework check for 1st domain
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soc/amd/common,genoa_poc/domain: rework check for 1st domain

Previously the code checked if the first downstream bus of the domain
was bus 0 in segment group 0 to only run certain code for the first
domain. Instead check if the domain number is 0 which should make the
code a bit easier to understand.

TEST=add_opensil_memmap still gets called exactly once on Onyx

Signed-off-by: Felix Held 
Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/genoa_poc/domain.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index f17346f..7bcc01b 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -254,7 +254,7 @@
    acpigen_resource_producer_bus_number(domain->downstream->secondary,
    				     domain->downstream->max_subordinate);

-	if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) {
+	if (domain->path.domain.domain == 0) {
    	/* ACPI 6.4.2.5 I/O Port Descriptor */
    	acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1,
    			   PCI_IO_CONFIG_PORT_COUNT, 1);
diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c
index 57e020a..653e2d2 100644
--- a/src/soc/amd/genoa_poc/domain.c
+++ b/src/soc/amd/genoa_poc/domain.c
@@ -18,7 +18,7 @@
    amd_pci_domain_read_resources(domain);

// We only want to add the DRAM memory map once
-	if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) {
+	if (domain->path.domain.domain == 0) {
    	/* 0x1000 is a large enough first index to be sure to not overlap with the
    	   resources added by amd_pci_domain_read_resources */
    	add_opensil_memmap(domain, 0x1000);