Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55786 )
Change subject: soc/intel/skylake: Use `is_devfn_enabled()` ......................................................................
soc/intel/skylake: Use `is_devfn_enabled()`
Use the `is_devfn_enabled()` function for the sake of brevity.
Change-Id: Ic848767799e165200f26c2d5a58fbd3b72b9c240 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/55786 Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/fsp_params.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 5 files changed, 24 insertions(+), 57 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 51fea18..7e06ffa 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -405,13 +405,12 @@
static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ const bool emit_igd = - igfx_dev && igfx_dev->enabled && + is_devfn_enabled(SA_DEVFN_IGD) && gfx_vtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4);
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d4e8341..f0ed699 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -283,8 +283,7 @@ } }
- dev = pcidev_path_on_root(PCH_DEVFN_SATA); - params->SataEnable = dev && dev->enabled; + params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); if (params->SataEnable) { memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); @@ -350,17 +349,13 @@ memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode));
- dev = pcidev_path_on_root(PCH_DEVFN_CIO); - params->PchCio2Enable = dev && dev->enabled; + params->PchCio2Enable = is_devfn_enabled(PCH_DEVFN_CIO);
- dev = pcidev_path_on_root(SA_DEVFN_IMGU); - params->SaImguEnable = dev && dev->enabled; + params->SaImguEnable = is_devfn_enabled(SA_DEVFN_IMGU);
- dev = pcidev_path_on_root(SA_DEVFN_CHAP); - tconfig->ChapDeviceEnable = dev && dev->enabled; + tconfig->ChapDeviceEnable = is_devfn_enabled(SA_DEVFN_CHAP);
- dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); - params->Heci3Enabled = dev && dev->enabled; + params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3);
params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX);
@@ -368,8 +363,7 @@ params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
- dev = pcidev_path_on_root(PCH_DEVFN_GBE); - params->PchLanEnable = dev && dev->enabled; + params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; @@ -378,12 +372,10 @@ } params->SsicPortEnable = config->SsicPortEnable;
- dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - params->ScsEmmcEnabled = dev && dev->enabled; + params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
- dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - params->ScsSdCardEnabled = dev && dev->enabled; + params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { params->PchScsEmmcHs400DllDataValid = @@ -395,20 +387,16 @@ }
/* If ISH is enabled, enable ISH elements */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev && dev->enabled; + params->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
- dev = pcidev_path_on_root(PCH_DEVFN_HDA); - params->PchHdaEnable = dev && dev->enabled; + params->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable;
- dev = pcidev_path_on_root(SA_DEVFN_TS); - params->Device4Enable = dev && dev->enabled; - dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); - params->PchThermalDeviceEnable = dev && dev->enabled; + params->Device4Enable = is_devfn_enabled(SA_DEVFN_TS); + params->PchThermalDeviceEnable = is_devfn_enabled(PCH_DEVFN_THERMAL);
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; @@ -467,8 +455,7 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev && dev->enabled; + params->ShowSpiController = is_devfn_enabled(PCH_DEVFN_SPI);
/* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -481,8 +468,7 @@ }
/* Enable or disable Gaussian Mixture Model in devicetree */ - dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev && dev->enabled; + params->GmmEnable = is_devfn_enabled(SA_DEVFN_GMM);
/* * Send VR specific mailbox commands: @@ -531,11 +517,7 @@ tconfig->VtdDisable = 0; }
- dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
params->PavpEnable = CONFIG(PAVP);
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index 294bf44..f05532c 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -27,7 +27,6 @@ FSP_M_TEST_CONFIG *m_t_cfg, const struct soc_intel_skylake_config *config) { - const struct device *dev; /* * To enable or disable the corresponding PEG root port you need to * add to the devicetree.cb: @@ -38,8 +37,7 @@ * If PEG port is not defined in the device tree, it will be disabled * in FSP */ - dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ - m_cfg->Peg0Enable = dev && dev->enabled; + m_cfg->Peg0Enable = is_devfn_enabled(SA_DEVFN_PEG0); if (m_cfg->Peg0Enable) { m_cfg->Peg0Enable = 2; m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; @@ -52,8 +50,7 @@ m_t_cfg->Peg0Gen3EqPh3Method = 0; }
- dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ - m_cfg->Peg1Enable = dev && dev->enabled; + m_cfg->Peg1Enable = is_devfn_enabled(SA_DEVFN_PEG1); if (m_cfg->Peg1Enable) { m_cfg->Peg1Enable = 2; m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; @@ -63,8 +60,7 @@ m_t_cfg->Peg1Gen3EqPh3Method = 0; }
- dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ - m_cfg->Peg2Enable = dev && dev->enabled; + m_cfg->Peg2Enable = is_devfn_enabled(SA_DEVFN_PEG2); if (m_cfg->Peg2Enable) { m_cfg->Peg2Enable = 2; m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; @@ -109,10 +105,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { - const struct device *dev; - - dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
/* * If iGPU is enabled, set IGD stolen size to 64MB. The FBC @@ -132,7 +125,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_skylake_config *config; - const struct device *dev; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
@@ -154,14 +146,12 @@ /* DCI and TraceHub configs */ m_t_cfg->PchDciEn = config->PchDciEn;
- dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - m_cfg->EnableTraceHub = dev && dev->enabled; + m_cfg->EnableTraceHub = is_devfn_enabled(PCH_DEVFN_TRACEHUB); m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = dev && dev->enabled; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
/* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 8996bce..4184331 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -12,8 +12,6 @@
static void systemagent_vtd_init(void) { - const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); if (!vtd_capable) @@ -23,7 +21,7 @@ pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF);
- if (igd_dev && igd_dev->enabled) + if (is_devfn_enabled(SA_DEVFN_IGD)) sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1);
sa_set_mch_bar(&soc_vtvc0_mmio_descriptor, 1); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 8b64435..2b29767 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -28,8 +28,6 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, "PCIEXBAR" }, @@ -44,7 +42,7 @@ ARRAY_SIZE(soc_fixed_resources));
if (soc_is_vtd_capable()) { - if (igd_dev && igd_dev->enabled) + if (is_devfn_enabled(SA_DEVFN_IGD)) sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1);
-
Werner Zeh (Code Review)