Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, Tim Chu.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70048 )
Change subject: sb,soc/intel/common: Add common get_pmbase() ......................................................................
sb,soc/intel/common: Add common get_pmbase()
Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/haswell/gma.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 46 files changed, 108 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70048/1
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 6e6948b..7e48f5c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -15,6 +15,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/lynxpoint/pch.h> #include <types.h>
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1c820c2..7e5f6ac 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -163,7 +163,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index 98843d1..7a00444 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -137,6 +137,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -162,7 +163,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 9389322..300ac71 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -250,12 +250,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 811c762..d601f93 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -98,7 +98,7 @@ const struct soc_intel_apollolake_config *cfg; cfg = config_of_soc();
- fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; + fadt->pm_tmr_blk = get_pmbase() + PM1_TMR;
fadt->pm_tmr_len = 4;
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c1dee0c..3cd5c8d 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -7,6 +7,7 @@ #include <acpi/acpi.h> #include <soc/gpe.h> #include <soc/iomap.h> +#include <southbridge/intel/common/pmbase.h>
/* ACPI_BASE_ADDRESS */
@@ -244,7 +245,4 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void);
-/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f474553..765b2c8 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -218,12 +218,6 @@ return rtc_failure; }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - void pmc_soc_set_afterg3_en(const bool on) { const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0b898a8..e6eebf4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -147,7 +147,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); const struct soc_intel_cannonlake_config *config; config = config_of_soc();
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 863d9f9..3b0c14d 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -156,8 +157,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7df8d47..2219f65 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -243,12 +243,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 860c868..ece3d11 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -107,7 +107,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
fadt->sci_int = acpi_sci_irq();
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 091b785..3842391 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -146,7 +146,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6a86787..4a3fde2 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -155,7 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 76a9cd3..7dee348 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 9781927..cc95445 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -143,7 +143,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 05db830..d4a385a 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -155,8 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 9297ffd..f1d4d21 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 369eb02..cf69825 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -146,7 +146,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index eea875b..d4a385a 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -155,7 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f2a4c90..7e00ca5 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index 54de566..f7d1de7 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -149,7 +149,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h index c486232..e23b96c 100644 --- a/src/soc/intel/meteorlake/include/soc/pm.h +++ b/src/soc/intel/meteorlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -156,7 +157,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 974f966..29ef32f 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -241,12 +241,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7a08c6e..408feb3 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -13,7 +13,5 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void);
-/* STM Support */ -uint16_t get_pmbase(void);
#endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index a1b3e43..99a02df 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -8,7 +8,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc();
fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index f0ce146..02bd555 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -8,6 +8,7 @@ #include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> #include <soc/smbus.h>
/* ACPI_BASE_ADDRESS / PMBASE */ @@ -186,7 +187,4 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); }
-/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index fe26ebf..c234e30 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -243,12 +243,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 573dc5f..68d2452 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -146,7 +146,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
config_t *config = config_of_soc();
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index cb0781a..d782464 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -137,6 +137,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
struct chipset_power_state { uint16_t pm1_sts; @@ -162,7 +163,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 9aca5c2..1fb2b07 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -265,12 +265,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index b4d6df9..a3f2d68 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -7,6 +7,7 @@ #include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h>
/* ACPI_BASE_ADDRESS / PMBASE */ #define PM1_STS 0x00 @@ -117,8 +118,6 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void);
-uint16_t get_pmbase(void); - void pmc_lock_smi(void);
#endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index c63285c..0051e04 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -159,12 +159,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); }
-/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 88f24d4..7358693 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -36,7 +36,7 @@
void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase();
/* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ fadt->flags &= ~(ACPI_FADT_SEALED_CASE); diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..ba7111b 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -11,9 +11,13 @@ #include "pmbase.h" #include "pmutil.h"
+#define PMSIZE 0x80 + +#if !CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) && !CONFIG(SOC_INTEL_BAYTRAIL) && \ + !CONFIG(SOC_INTEL_BRASWELL) + /* LPC PM Base Address Register */ #define PMBASE 0x40 -#define PMSIZE 0x80
u16 lpc_get_pmbase(void) { @@ -21,57 +25,67 @@ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xfffc; #else + return pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; +#endif +} +#endif + +#if HAVE_DYNAMIC_ACPI_BASE_ADDRESS +u16 get_pmbase(void) +{ static u16 pmbase;
+ if (ENV_SMM) + return lpc_get_pmbase(); + if (pmbase) return pmbase; - - pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; + pmbase = lpc_get_pmbase();
return pmbase; -#endif } +#endif
void write_pmbase32(const u8 addr, const u32 val) { ASSERT(addr <= (PMSIZE - sizeof(u32)));
- outl(val, lpc_get_pmbase() + addr); + outl(val, get_pmbase() + addr); }
void write_pmbase16(const u8 addr, const u16 val) { ASSERT(addr <= (PMSIZE - sizeof(u16)));
- outw(val, lpc_get_pmbase() + addr); + outw(val, get_pmbase() + addr); }
void write_pmbase8(const u8 addr, const u8 val) { ASSERT(addr <= (PMSIZE - sizeof(u8)));
- outb(val, lpc_get_pmbase() + addr); + outb(val, get_pmbase() + addr); }
u32 read_pmbase32(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u32)));
- return inl(lpc_get_pmbase() + addr); + return inl(get_pmbase() + addr); }
u16 read_pmbase16(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u16)));
- return inw(lpc_get_pmbase() + addr); + return inw(get_pmbase() + addr); }
u8 read_pmbase8(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u8)));
- return inb(lpc_get_pmbase() + addr); + return inb(get_pmbase() + addr); }
int acpi_get_sleep_type(void) diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index febcff2..451c3f5 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -1,9 +1,50 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __INTEL_COMMON_PMBASE__ +#define __INTEL_COMMON_PMBASE__ + #include <stdint.h>
+/* FIXME: ENV_SMM must reload base on each entry to SMI ? */ +#define HAVE_DYNAMIC_ACPI_BASE_ADDRESS ENV_SMM + u16 lpc_get_pmbase(void);
+/* FIXME: Implement <soc/iomap.h>, only DEFAULT_PMBASE needed. + We already have <soc/nvs.h> for similar case on GNVS. */ +#if CONFIG(SOUTHBRIDGE_INTEL_I82371EB) +#include <southbridge/intel/i82371eb/i82371eb.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801DX) +#include <southbridge/intel/i82801dx/i82801dx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/i82801gx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX) +#include <southbridge/intel/i82801ix/i82801ix.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801JX) +#include <southbridge/intel/i82801jx/i82801jx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || CONFIG(SOUTHBRIDGE_INTEL_C216) +#include <southbridge/intel/bd82x6x/pch.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) +#include <southbridge/intel/lynxpoint/pch.h> +#else + +/* ENV_SMM can use static value if PM BAR is locked? */ +#undef HAVE_DYNAMIC_ACPI_BASE_ADDRESS +#define HAVE_DYNAMIC_ACPI_BASE_ADDRESS 0 + +#include <soc/iomap.h> +#define DEFAULT_PMBASE ACPI_BASE_ADDRESS +#endif + +#if HAVE_DYNAMIC_ACPI_BASE_ADDRESS +u16 get_pmbase(void); +#else +static __always_inline u16 get_pmbase(void) +{ + return DEFAULT_PMBASE; +} +#endif + void write_pmbase32(const u8 addr, const u32 val); void write_pmbase16(const u8 addr, const u16 val); void write_pmbase8(const u8 addr, const u8 val); @@ -11,3 +52,5 @@ u32 read_pmbase32(const u8 addr); u16 read_pmbase16(const u8 addr); u8 read_pmbase8(const u8 addr); + +#endif diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 744b1c1..9c06112 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -114,8 +114,6 @@ #define TCO2_CNT 0x6a #endif
-u16 get_pmbase(void); - u16 reset_pm1_status(void); void dump_pm1_status(u16 pm1_sts); void dump_tco_status(u32 tco_sts); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index a6e000b..00441ce 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -10,11 +10,6 @@
#include "pmutil.h"
-u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - static int smi_enabled(void) { u32 smi_en; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f1..c7853eb 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,11 +17,6 @@
#include "pmutil.h"
-u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - void gpi_route_interrupt(u8 gpi, u8 mode) { u32 gpi_rout; diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index a775146..fa06759 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include <stdint.h> #include <elog.h> diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 2051223..d9e3619 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -3,6 +3,7 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/lynxpoint/pch.h> #include "chip.h"
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b8e9d5f..3476db2 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -17,6 +17,7 @@ #include "pch.h" #include <acpi/acpigen.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba_pirq.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8f7cdb8..448f74c8 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include <southbridge/intel/common/pmbase.h> #include "iobp.h" #include "pch.h"
@@ -56,14 +57,9 @@ return PCH_TYPE_DESKTOP; }
-u16 get_pmbase(void) +u16 lpc_get_pmbase(void) { - static u16 pmbase; - - if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; - return pmbase; + return pci_read_config16(pch_get_lpc_device(), PMBASE) & 0xfffc; }
u16 get_gpiobase(void) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 3ed434a..3f78534 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -120,7 +120,6 @@ enum pch_platform_type get_pch_platform_type(void); int pch_silicon_revision(void); int pch_silicon_id(void); -u16 get_pmbase(void); u16 get_gpiobase(void);
/* Power Management register handling in pmutil.c */ diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index dd7f199..fa62eca 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -12,6 +12,7 @@ #include <console/console.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rtc.h> #include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 280235f..327058f 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -6,6 +6,7 @@ #include <arch/io.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h>
#include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 769cacb..8edd986 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -12,6 +12,7 @@ #include <halt.h> #include <option.h> #include <southbridge/intel/common/finalize.h> +#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> #include <soc/nvs.h>
-
Kyösti Mälkki (Code Review)