Change in coreboot[master]: intel/fsp: Update cannonlake fsp header

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25378

Change subject: intel/fsp: Update cannonlake fsp header
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intel/fsp: Update cannonlake fsp header

Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17
Offset 15h Speed report incorrectly issue.

BUG=None
TEST=Boot up with meowth platform and run dmidecode to see two dimm
entries under Type 17.

Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e
Signed-off-by: Lijian Zhao 
---
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/25378/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
index 941a891..99dd815 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
@@ -202,6 +202,7 @@
   UINT8            SpdModuleType;           ///< Save SPD ModuleType information needed for SMBIOS structure creation.
   UINT8            SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
   UINT8            SpdSave[MAX_SPD_SAVE];   ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+  UINT16           Speed;                   ///< The maximum capable speed of the device, in MHz.
 } DIMM_INFO;

typedef struct {