[S] Change in coreboot[master]: drivers/intel/fsp2_0: Have provision for caching TOM region

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73334 )

Change subject: drivers/intel/fsp2_0: Have provision for caching TOM region
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drivers/intel/fsp2_0: Have provision for caching TOM region

This patch enables early caching of TOM region to optimize the boot
time if valid mrc cache is found (i.e. except the first boot after
flashing/updating few AP firmware image).

TEST=Able to build and boot google/rex to ChromeOS.

Signed-off-by: Subrata Banik 
Change-Id: Ia575ad0f99d5b0fd015e40b0862e8560700f6c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73334
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 29 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index dcb44f6..4f0dbf6 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -24,6 +24,10 @@
 #include <types.h>
 #include <vb2_api.h>

+#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)
+#include <intelbasecode/tom.h>
+#endif
+
 static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));

static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
@@ -255,6 +259,12 @@
    	die_with_post_code(POST_INVALID_VENDOR_BINARY,
    		"FSPM_ARCH_UPD not found!\n");

+	/* Early caching of TOM region if valid mrc cache data is found */
+#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM))
+	if (arch_upd->NvsBufferPtr)
+		early_tom_enable_cache_range();
+#endif
+
    /* Give SoC and mainboard a chance to update the UPD */
    platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);