Change in coreboot[master]: soc/intel/tigerlake: Send End-of-Post message to CSE

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55632 )

Change subject: soc/intel/tigerlake: Send End-of-Post message to CSE
......................................................................

soc/intel/tigerlake: Send End-of-Post message to CSE

This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command.

TEST=autotest firmware_CheckEOPState confirms ME is in post-boot state

Signed-off-by: Tim Wawrzynczak 
Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/55632/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4ec163b..9a1f579 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -69,6 +69,7 @@
    select SOC_INTEL_COMMON_PCH_BASE
    select SOC_INTEL_COMMON_RESET
    select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+	select SOC_INTEL_CSE_SET_EOP
    select SSE2
    select SUPPORT_CPU_UCODE_IN_CBFS
    select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 823f8e5..fa02221 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -199,7 +199,7 @@
    }

/* Enable End of Post in PEI phase */
-	params->EndOfPostMessage = EOP_PEI;
+	params->EndOfPostMessage = EOP_DISABLE;

/* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {