Hello Tim Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to review the following change.
Change subject: mb/google/puff: Update DPTF parameters ......................................................................
mb/google/puff: Update DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 126 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/1
diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl index 2c44a82..3cecc6c 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -1 +1,126 @@ -#include <baseboard/acpi/dptf.asl> +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + _SB.DPTF.TFN1, _SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +})
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+2
Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+1
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Update DPTF parameters ......................................................................
Patch Set 1:
Hi Google team, Could you help to merge and cherry-pick this CL to chromium server? Thanks
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Update DPTF parameters ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG@7 PS1, Line 7: mb/google/puff: Update DPTF parameters Add variant specific DPTF parameters
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG@14 PS1, Line 14: boot on puff board Fits on the line above.
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 38: #define DPTF_TSR1_ACTIVE_AC0 50 Please use tabs as above.
Hello build bot (Jenkins), Edward O'Callaghan, Tim Chen, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#2).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 126 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/2
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG@7 PS1, Line 7: mb/google/puff: Update DPTF parameters
Add variant specific DPTF parameters
Done
https://review.coreboot.org/c/coreboot/+/40282/1//COMMIT_MSG@14 PS1, Line 14: boot on puff board
Fits on the line above.
Done
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 38: #define DPTF_TSR1_ACTIVE_AC0 50
Please use tabs as above.
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 13: */ Please use SPDX license header.
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 13: */
Please use SPDX license header.
Could you provide the header? I'm not sure which is the correct format. Thanks.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 13: */
Could you provide the header? I'm not sure which is the correct format. […]
Use the one from the baseboard file?
/* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
Hello build bot (Jenkins), Edward O'Callaghan, Tim Chen, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#3).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/3
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/40282/1/src/mainboard/google/hatch/... PS1, Line 13: */
Use the one from the baseboard file? […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 3: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 3: Code-Review+1
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 3: Code-Review+2
Tim Chen has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Removed Code-Review+2 by Tim Chen tim-chen@quanta.corp-partner.google.com
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#4).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/4
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#5).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/5
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#6).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/6
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#7).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 127 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/7
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#8).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 126 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/8
Hello build bot (Jenkins), Paul Menzel, Edward O'Callaghan, Tim Chen, Angel Pons, Kangheui Won, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40282
to look at the new patch set (#10).
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/40282/10
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 11: Code-Review+1
Tim Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 11:
below is reply in mail thread from Intel/James
Hi Antony, It’s ok for all power limit setting. and Ryan please help +1 on the CL accordingly. Thanks
Could Google team help to +2 and merge this CL? Thank you.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 11: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 11: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
mb/google/puff: Add variant specific DPTF parameters
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl 1 file changed, 115 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Chen: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl index 2c44a82..de12ee1 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -1 +1,115 @@ -#include <baseboard/acpi/dptf.asl> +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + _SB.DPTF.TFN1, _SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + _SB.DPTF.TFN1, _SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +})
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40282 )
Change subject: mb/google/puff: Add variant specific DPTF parameters ......................................................................
Patch Set 12:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2368 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2367 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2366
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Edward O'Callaghan (Code Review)
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Paul Menzel (Code Review)
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Peter Ou (Code Review)
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Tim Chen (Code Review)