Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31037
Change subject: mb/google/sarien/variants: Set tcc offset value ......................................................................
mb/google/sarien/variants: Set tcc offset value
Set tcc offset value to 5 degree celsius for Sarien system.
BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system
Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31037/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ff26cbf..98009f0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -65,6 +65,9 @@ #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "5" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 59f1f30..76e5db7 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -75,7 +75,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "3" + register "tcc_offset" = "5"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31037 )
Change subject: mb/google/sarien/variants: Set tcc offset value ......................................................................
Patch Set 1: Code-Review+2
Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31037 )
Change subject: mb/google/sarien/variants: Set tcc offset value ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31037 )
Change subject: mb/google/sarien/variants: Set tcc offset value ......................................................................
mb/google/sarien/variants: Set tcc offset value
Set tcc offset value to 5 degree celsius for Sarien system.
BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system
Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/31037 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Naresh Solanki naresh.solanki@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Naresh Solanki: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index af8fe18..2b0408e 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -70,6 +70,9 @@ #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "5" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 59f1f30..76e5db7 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -75,7 +75,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "3" + register "tcc_offset" = "5"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
-
Duncan Laurie (Code Review) -
Naresh Solanki (Code Review)
-
Patrick Georgi (Code Review)
-
Sumeet R Pawnikar (Code Review)