[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email )

Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot
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Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/84996/comment/c240330e_7155d01e?usp... :
PS1, Line 200: if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
When you come out of global_reset, is the previous state S5? If not, then we will never end up disabling UFS.

Atleast on my testing, the previous sleep state is not showing as S5.

```
␛[0m[INFO ]  cse_lite: Set Boot Partition Info Command (RW)␛[0m
␛[0m[DEBUG]  HECI: Global Reset(Type:1) Command␛[0m
␀␛[0m
␛[0m
␛[1m[NOTE ]  coreboot-v1.9308_26_0.0.22-38623-g629ff30d2834 Sat Oct 19 18:42:55 UTC 2024 x86_32 romstage starting (log level: 8)...␛[0m
␛[0m[DEBUG]  pm1_sts: 8000 pm1_en: 0000 pm1_cnt: 00000000␛[0m
␛[0m[DEBUG]  gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000␛[0m
␛[0m[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000␛[0m
␛[0m[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000␛[0m
␛[0m[DEBUG]  gpe0_sts[3]: 00014040 gpe0_en[3]: 00000000␛[0m
␛[0m[DEBUG]  TCO_STS:   0000 0000␛[0m
␛[0m[DEBUG]  GEN_PMCON: d9801038 00002200␛[0m
␛[0m[DEBUG]  GBLRST_CAUSE: 00000040 00000000␛[0m
␛[0m[DEBUG]  HPR_CAUSE0: 00000000␛[0m
␛[0m[DEBUG]  prev_sleep_state 0 (S0)␛[0m
```