[M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Reka Norman (Code Review)]

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> So does it spend time flushing data from the cache that was never dirty to begin with? That sounds w […]

My guess is that it just takes that long to iterate through the region and run CLFLUSH on every cache line, even when most of them don't actually write back. 7 MiB of data (~5 MiB cbmem + 2 MiB stage cache) with 64 byte cache lines is over 100k CLFLUSH instructions.

I was curious so I did some tests. I duplicated the CLFLUSH loop and measured how long the first and second loops take to flush the stage cache region in different scenarios.

Umodified (only thing in stage cache is 23K postcar):
 611:<unknown>                                         900,724 (3,402)
 612:<unknown>                                         903,971 (3,246)

Don't add postcar to stage cache, so stage cache should be clean:
 611:<unknown>                                         888,219 (3,237)
 612:<unknown>                                         891,465 (3,245)

memset all 2M of stage cache:
 611:<unknown>                                         911,394 (9,211)
 612:<unknown>                                         914,654 (3,260)

So that seems to support my theory.