Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index ca66095..f348a20 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 891b782..a1c1be6 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
+#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -37,8 +42,9 @@ SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 512K) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 512K)
BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h new file mode 100644 index 0000000..a7feee7 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620e..e3bc622 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h>
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +}
Roger Lu has uploaded a new patch set (#2) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c M src/soc/mediatek/mt8192/spm.c 5 files changed, 26 insertions(+), 456 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/2
Roger Lu has uploaded a new patch set (#3) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8192/mmu_operations.c 3 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/3
Roger Lu has uploaded a new patch set (#4) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/4
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 4: Code-Review+1
Roger Lu has uploaded a new patch set (#5) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/5
Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47293
to look at the new patch set (#6).
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/6
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 6: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 8:
why can't we use DMA_COHERENT ?
Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47293
to look at the new patch set (#10).
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/10
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 10:
Patch Set 8:
why can't we use DMA_COHERENT ?
The SPM binary requires about 10KB buffer to load from CBFS. 1MB is too large for SPM. But I think this region can be shared with other drivers which support DMA mode.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 10:
The SPM DMA can be abandoned after it's fully loaded right? I wonder if we can leverage the MCU region for it, and always load SPM before MCU.
But anyway, given we're loading more and more blobs, I agree having a post-DRAM DMA maybe the better idea.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 10: Code-Review+2
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
Patch Set 10:
Patch Set 10:
The SPM DMA can be abandoned after it's fully loaded right? I wonder if we can leverage the MCU region for it, and always load SPM before MCU.
Yes, I did try the MCU region and SPM DMA hardware also works fine with MCU region.
But anyway, given we're loading more and more blobs, I agree having a post-DRAM DMA maybe the better idea.
Thank you.
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47293 )
Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ......................................................................
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware.
TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin yidi.lin@mediatek.com Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 07a13af..421968d 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 57b258c..c016d5f 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
+#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -41,8 +46,9 @@ SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 256K) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K)
BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h new file mode 100644 index 0000000..a7feee7 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620e..e3bc622 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h>
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +}
-
Hung-Te Lin (Code Review) -
Roger Lu (Code Review)
-
Yidi Lin (Code Review)
-
Yu-Ping Wu (Code Review)