Hello Wonkyu Kim, Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39420
to review the following change.
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
mb/google/volteer: Enable pcie rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.com Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb... Tested-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39420/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 070e4f6..cb704c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,10 @@ register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0"
+ # Enable Optane PCIE 11 using clk 0 + register "PcieRpEnable[10]" = "1" + register "HybridStorageMode" = "1" + # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" @@ -312,7 +316,7 @@
device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.4 off end # RP13 0xA0B4 device pci 1d.5 off end # RP14 0xA0B5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39420 )
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
Patch Set 1: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39420 )
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
Patch Set 1: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39420 )
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
Patch Set 1: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39420 )
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
Patch Set 1:
please set topic to TGL_UPSTREAM.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39420 )
Change subject: mb/google/volteer: Enable pcie rp11 for optane ......................................................................
mb/google/volteer: Enable pcie rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.com Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb... Tested-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b08ff7d..a65e5f1 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,10 @@ register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0"
+ # Enable Optane PCIE 11 using clk 0 + register "PcieRpEnable[10]" = "1" + register "HybridStorageMode" = "1" + # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" @@ -311,7 +315,7 @@
device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.4 off end # RP13 0xA0B4 device pci 1d.5 off end # RP14 0xA0B5
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Caveh Jalali (Code Review) -
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Wonkyu Kim (Code Review)