Change in coreboot[master]: soc/intel/*/pmutil.c: Align cosmetics across platforms

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50931 )

Change subject: soc/intel/*/pmutil.c: Align cosmetics across platforms
......................................................................

soc/intel/*/pmutil.c: Align cosmetics across platforms

Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931
Reviewed-by: Michael Niewöhner 
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/pmutil.c
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/elkhartlake/pmutil.c
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/jasperlake/pmutil.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/tigerlake/pmutil.c
7 files changed, 28 insertions(+), 47 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c
index 43d5084..d8308b4 100644
--- a/src/soc/intel/alderlake/pmutil.c
+++ b/src/soc/intel/alderlake/pmutil.c
@@ -209,10 +209,8 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
     * S5 because the PCH does not set the WAK_STS bit when waking
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index b2dbfbe..bf4e34f 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -202,15 +202,13 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
    if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
    	prev_sleep_state = ACPI_S5;

@@ -241,8 +239,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

pmc = pmc_mmio_regs();
    ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c
index b969ba5..e54da43 100644
--- a/src/soc/intel/elkhartlake/pmutil.c
+++ b/src/soc/intel/elkhartlake/pmutil.c
@@ -202,15 +202,13 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
    if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
    	prev_sleep_state = ACPI_S5;

@@ -241,8 +239,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

pmc = pmc_mmio_regs();
    ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 263bfa2..9cc6f02 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -202,15 +202,13 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
    if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
    	prev_sleep_state = ACPI_S5;

@@ -241,8 +239,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

pmc = pmc_mmio_regs();
    ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
index 7a42d77..3b93d32 100644
--- a/src/soc/intel/jasperlake/pmutil.c
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -202,15 +202,13 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
    if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
    	prev_sleep_state = ACPI_S5;

@@ -241,8 +239,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

pmc = pmc_mmio_regs();
    ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 6d16f52..906a1cf 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -204,8 +204,7 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-						int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
    /*
     * Check for any power failure to determine if this a wake from
@@ -242,8 +241,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	       ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
    ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 39fc36b..c980a2c 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -208,15 +208,13 @@
 }

/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
-	int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 {
-
    /*
     * Check for any power failure to determine if this a wake from
-	* S5 because the PCH does not set the WAK_STS bit when waking
-	* from a true G3 state.
-	*/
+	 * S5 because the PCH does not set the WAK_STS bit when waking
+	 * from a true G3 state.
+	 */
    if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
    	prev_sleep_state = ACPI_S5;

@@ -247,8 +245,7 @@
    ps->tco1_sts = tco_read_reg(TCO1_STS);
    ps->tco2_sts = tco_read_reg(TCO2_STS);

-	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
-	ps->tco1_sts, ps->tco2_sts);
+	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);

pmc = pmc_mmio_regs();
    ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);