New patch to review for coreboot: 056b0ff superio/ite/it8718f: Remove hard coding from romstage
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5717
-gerrit
commit 056b0ff6f5f9399d7be1ac877ea742b0027a5f85 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon May 12 05:02:58 2014 +1000
superio/ite/it8718f: Remove hard coding from romstage
Make use of common ITE superio framework and there-by removing any hard coding of superio base address.
Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/gigabyte/ma785gm/romstage.c | 3 ++- src/mainboard/gigabyte/ma785gmt/romstage.c | 3 ++- src/mainboard/gigabyte/ma78gm/romstage.c | 3 ++- src/superio/ite/it8718f/early_serial.c | 43 +++--------------------------- src/superio/ite/it8718f/it8718f.h | 6 ++--- 5 files changed, 12 insertions(+), 46 deletions(-)
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bfc50b6..a437009 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV);
console_init();
diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index deef840..85854c2 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,49 +21,12 @@ #include <arch/io.h> #include "it8718f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8718f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8718f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8718f_exit_conf(void) -{ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); -} - - /* * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(void) +void it8718f_disable_reboot(device_t dev) { - it8718f_enter_conf(); - it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); - it8718f_exit_conf(); + ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 018f08a..61c75cf 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -21,6 +21,8 @@ #ifndef SUPERIO_ITE_IT8718F_H #define SUPERIO_ITE_IT8718F_H
+#include <arch/io.h> + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
#define IT8718F_FDC 0x00 /* Floppy */ @@ -33,8 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */
-#if defined(__PRE_RAM__) -void it8718f_disable_reboot(void); -#endif +void it8718f_disable_reboot(device_t dev);
#endif /* SUPERIO_ITE_IT8718F_H */
-
Edward O'Callaghan