Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )

Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................

Patch Set 14:

(2 comments)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/55364/comment/b9827a71_8dd10864 
PS12, Line 145: cse_fw_sync() must be called after DRAM initialization as
              : 		 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
              : 		 * is expected to be executed after DRAM initialization.
> Thanks for explanation and can you please write the same to the commit msg for record so folks don't […]

Ack

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/55364/comment/063b221e_a9664571 
PS13, Line 135: timestamp_add_now(TS_BEFORE_CSE_FW_SYNC);
> nit: you can submit timestamp CL separately if you wish ? […]

Correct , I will allow the original patch(without timestamp) land in upstream and also need clarification from community on TS ids to be used here. I will push cse fw sync timestamp patch separately once I get the feedback.