Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c
Other Intel southbridges do this.
Change-Id: I8306295fb87776aab5ed0e56e1a9c480c65fe3c6 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 136 insertions(+), 128 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/43372/1
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index bd7f93c..d8de593e 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -6,6 +6,7 @@
ramstage-y += pch.c ramstage-y += azalia.c +ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += ../bd82x6x/pci.c ramstage-y += ../bd82x6x/pcie.c diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c new file mode 100644 index 0000000..7efeae3 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmutil.h> +#include "chip.h" + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + + fadt->sci_int = 0x9; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2c29046..7e99613 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -576,134 +576,6 @@ } }
-void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - struct device *dev = pcidev_on_root(0x1f, 0); - config_t *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; - - - fadt->sci_int = 0x9; - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; - /* flush_* is ignored if ACPI_FADT_WBINVD is set */ - fadt->flush_size = 0; - fadt->flush_stride = 0; - /* P_CNT not supported */ - fadt->duty_offset = 0; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - if (chip->docking_supported) { - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB";
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/fadt.c:
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 42: if (!c2_latency) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 64: if (chip->docking_supported) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 67: if (c2_latency < 100) { braces {} are not necessary for single statement blocks
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
Patch Set 1:
(12 comments)
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/fadt.c:
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 71: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 80: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 87: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 90: 0 ACPI_ACCESS_SIZE_UNDEFINED
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 94: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 101: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 104: 0 ACPI_ACCESS_SIZE_UNDEFINED
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 108: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 115: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 122: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 129: 1 ACPI_ADDRESS_SPACE_IO
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 132: 0 ACPI_ACCESS_SIZE_UNDEFINED
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
Patch Set 1:
(12 comments)
I'm not going to replace any numbers with macros in changes like these. They usually aren't reproducible, even though I'm just cutting and pasting code around. Doing changes would only make review harder. Plus, I plan on factoring most of these values out at some point, so I'd rather use the definitions at the end of the clean-up.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/fadt.c:
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 71: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 80: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 87: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 90: 0
ACPI_ACCESS_SIZE_UNDEFINED
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 94: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 101: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 104: 0
ACPI_ACCESS_SIZE_UNDEFINED
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 108: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 115: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 122: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch.
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 129: 1
ACPI_ADDRESS_SPACE_IO
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
https://review.coreboot.org/c/coreboot/+/43372/1/src/southbridge/intel/ibexp... PS1, Line 132: 0
ACPI_ACCESS_SIZE_UNDEFINED
Out of the scope of this patch. Also, did you notice that this is actually useless, and is going to be removed on follow-ups?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43372 )
Change subject: sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c ......................................................................
sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c
Other Intel southbridges do this.
Change-Id: I8306295fb87776aab5ed0e56e1a9c480c65fe3c6 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43372 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 136 insertions(+), 128 deletions(-)
Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index bd7f93c..d8de593e 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -6,6 +6,7 @@
ramstage-y += pch.c ramstage-y += azalia.c +ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += ../bd82x6x/pci.c ramstage-y += ../bd82x6x/pcie.c diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c new file mode 100644 index 0000000..7efeae3 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmutil.h> +#include "chip.h" + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + + fadt->sci_int = 0x9; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2c29046..7e99613 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -576,134 +576,6 @@ } }
-void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - struct device *dev = pcidev_on_root(0x1f, 0); - config_t *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; - - - fadt->sci_int = 0x9; - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; - /* flush_* is ignored if ACPI_FADT_WBINVD is set */ - fadt->flush_size = 0; - fadt->flush_stride = 0; - /* P_CNT not supported */ - fadt->duty_offset = 0; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - if (chip->docking_supported) { - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB";