Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28956
Change subject: src: Standardize PCI_DEV(0, 0x1f, 0) name ......................................................................
src: Standardize PCI_DEV(0, 0x1f, 0) name
Change-Id: I0be00e5e9c733bbeb863250bd51eea8d33f54300 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/bootblock.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/asus/p8h61-m_pro/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x201/dock.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/fsp_sandybridge/report_platform.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c M src/soc/intel/denverton_ns/include/soc/lpc.h M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/fsp_bd82x6x/early_init.c M src/southbridge/intel/fsp_bd82x6x/early_me.c M src/southbridge/intel/fsp_bd82x6x/finalize.c M src/southbridge/intel/fsp_bd82x6x/gpio.c M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_i89xx/early_init.c M src/southbridge/intel/fsp_i89xx/early_me.c M src/southbridge/intel/fsp_i89xx/finalize.c M src/southbridge/intel/fsp_i89xx/gpio.c M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_i89xx/romstage.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/gpio.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/finalize.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/pch.h 87 files changed, 280 insertions(+), 280 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28956/1
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 327c4a4..a5a2ae7 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -38,7 +38,7 @@ * Hard Reset */ if ((inb(0xcf9) == 0x04) || - (pci_io_read_config32(SOC_LPC_DEV, RCBA) + (pci_io_read_config32(LPC_DEV, RCBA) & RCBA_ENABLE)) { outb(0x00, 0xcf9); outb(0x06, 0xcf9); diff --git a/src/mainboard/adi/rcc-dff/romstage.c b/src/mainboard/adi/rcc-dff/romstage.c index c7c78e2..e69178a 100644 --- a/src/mainboard/adi/rcc-dff/romstage.c +++ b/src/mainboard/adi/rcc-dff/romstage.c @@ -28,7 +28,7 @@
static void interrupt_routing_config(void) { - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); + u8 *ilb_base = (u8 *)(pci_read_config32(LPC_DEV, IBASE) & ~0xf);
/* * Initialize Interrupt Routings for each device in ilb_base_address. diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 050d6c5..bc57090 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -22,9 +22,9 @@
void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index d32b6f9..692cb78 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -42,7 +42,7 @@
void pch_enable_lpc(void) { - pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); + pci_or_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c index 76fc8aa..03797aa 100644 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ b/src/mainboard/asus/p8h61-m_lx/romstage.c @@ -44,7 +44,7 @@
void pch_enable_lpc(void) { - pci_or_config16(PCH_LPC_DEV, LPC_EN, + pci_or_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c index a6785ed..3d81595 100644 --- a/src/mainboard/asus/p8h61-m_pro/romstage.c +++ b/src/mainboard/asus/p8h61-m_pro/romstage.c @@ -26,7 +26,7 @@ void pch_enable_lpc(void) { /* Enable the Super IO */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); }
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 7e59d95..ad3abd2 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -23,7 +23,7 @@
void pch_enable_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 543e765..17bddab 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -32,13 +32,13 @@
void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 1ca6551..8eaf369 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -32,13 +32,13 @@
void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index f1cd176..2ec605e 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -24,10 +24,10 @@
void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x10); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d68a46c..7e4740d 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -40,13 +40,13 @@ { /* EC Decode Range Port60/64 and Port62/66 */ /* Enable EC and PS/2 Keyboard/Mouse*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
/* EC Decode Range Port68/6C */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
/* EC Decode Range Port 380-387 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
}
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 495c80e..668e27b 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -50,16 +50,16 @@ return;
/* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 163f4c3..1c54ef0 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -38,13 +38,13 @@ { /* Parrot EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
/* Map EC_IO decode to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
/* Map EC registers 68/6C decode to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d56dfd4..0a58838 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -46,11 +46,11 @@ * PS/2 Keyboard/Mouse Port60/64 * FDD Port3F0h-3F5h and Port3F7h */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | FDD_LPC_EN);
/* Stout EC Decode Range Port68/6C */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index b2095b9..13312c1 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -26,10 +26,10 @@ * CNF2 and CNF1 for Super I/O * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index c6d9a7c..7e6820a 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -25,10 +25,10 @@ * CNF2 and CNF1 for Super I/O * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index b97d5e4..efba86c 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -30,12 +30,12 @@ * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC * Enable parallel port and serial port */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index bb9298c..44804f3 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -29,12 +29,12 @@ * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC * Enable parallel port and serial port */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 75c2db0..d24e236 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -30,12 +30,12 @@ * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC * Enable parallel port and serial port */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 2197f2d..b6c8af4 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -35,12 +35,12 @@ * Enable SuperIO, TPM, Keyboard, LPT, COMA * (COMB can be equip on expansion header) */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
/* COMA: 3F8h, COMB: 2F8h */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 1994c4f..fe6fdec 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -27,11 +27,11 @@ * CNF2 and CNF1 for Super I/O * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index c70660a..7553398 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -30,11 +30,11 @@ * CNF2 and CNF1 for Super I/O * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c0201); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9d3b478..2c8dd239d 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -49,7 +49,7 @@
static void pch_enable_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); @@ -182,8 +182,8 @@ pch_enable_lpc();
/* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&gpio_map); setup_sio_gpios();
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a672294..132a565 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -36,7 +36,7 @@
void pch_enable_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/littleplains/romstage.c b/src/mainboard/intel/littleplains/romstage.c index c7c78e2..e69178a 100644 --- a/src/mainboard/intel/littleplains/romstage.c +++ b/src/mainboard/intel/littleplains/romstage.c @@ -28,7 +28,7 @@
static void interrupt_routing_config(void) { - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); + u8 *ilb_base = (u8 *)(pci_read_config32(LPC_DEV, IBASE) & ~0xf);
/* * Initialize Interrupt Routings for each device in ilb_base_address. diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index c7c78e2..e69178a 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -28,7 +28,7 @@
static void interrupt_routing_config(void) { - u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf); + u8 *ilb_base = (u8 *)(pci_read_config32(LPC_DEV, IBASE) & ~0xf);
/* * Initialize Interrupt Routings for each device in ilb_base_address. diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f7251a5..22040ac 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -35,14 +35,14 @@ void pch_enable_lpc(void) { /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0070);
/* Enable KBC on 0x06/0x64 (KBC), * EC on 0x62/0x66 (MC), * EC on 0x20c-0x20f (GAMEH), * Super I/O on 0x2e/0x2f (CNF1), * COM1/COM3 decode ranges. */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | GAMEH_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index bef2562..3027e5c 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -53,14 +53,14 @@ { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index be8052c..ea9b66b 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -55,14 +55,14 @@ { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 90d0886..7e6b49d 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -53,10 +53,10 @@ { /* EC Decode Range Port60/64, Port62/66 */ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1); }
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 633ba3f..b421c6b 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -28,14 +28,14 @@ { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 4fcd651..5d168fd 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -65,14 +65,14 @@ { /* T520 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 88e07c1..06b8c5f 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -57,14 +57,14 @@ { /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..983db10 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -24,13 +24,13 @@ { /* EC Decode Range Port60/64, Port62/66 */ /* Enable TPM, EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x007c1611); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0x00040069); + pci_write_config32(LPC_DEV, LPC_GEN3_DEC, 0x000c0701); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x000c06a1); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index a34d1db..7d798f7 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -38,14 +38,14 @@ { /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index a11c720..26a5a93 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -37,7 +37,7 @@
void dock_connect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc;
ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); @@ -48,7 +48,7 @@
void dock_disconnect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc;
ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); @@ -59,7 +59,7 @@
int dock_present(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; u8 st = inb(gpiobase + 0x0c);
return ((st >> 3) & 7) != 7; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8752949..d241422 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -47,25 +47,25 @@ { /* X201 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | GAMEL_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN3_DEC, 0x1c1681); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); + pci_write_config32(LPC_DEV, 0xd0, 0x0); + pci_write_config32(LPC_DEV, 0xdc, 0x8);
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + pci_write_config8(LPC_DEV, GEN_PMCON_3, + (pci_read_config8(LPC_DEV, GEN_PMCON_3) & ~2) | 1);
- pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + pci_write_config32(LPC_DEV, ETR3, + pci_read_config32(LPC_DEV, ETR3) & ~ETR3_CF9GR); }
static void rcba_config(void) @@ -194,8 +194,8 @@ ec_set_bit(0x3b, 4);
/* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
@@ -249,8 +249,8 @@ write_acpi16(0x0, 0x900); write_acpi32(0x20, 0xffff7ffe); write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); + pci_write_config8(LPC_DEV, GEN_PMCON_3, + pci_read_config8(LPC_DEV, GEN_PMCON_3) | 2); }
early_thermal_init(); diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 96e0284..3702462 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -38,14 +38,14 @@ { /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1ddaedf..2350196 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -36,14 +36,14 @@ { /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
- pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + pci_write_config32(LPC_DEV, ETR3, 0x10000); }
void mainboard_rcba_config(void) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 56f11a1..adb0cec 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -44,22 +44,22 @@ static void pch_enable_lpc(void) { /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); + pci_write_config32(LPC_DEV, 0xd0, 0x0); + pci_write_config32(LPC_DEV, 0xdc, 0x8);
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + pci_write_config8(LPC_DEV, GEN_PMCON_3, + (pci_read_config8(LPC_DEV, GEN_PMCON_3) & ~2) | 1);
- pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + pci_write_config32(LPC_DEV, ETR3, + pci_read_config32(LPC_DEV, ETR3) & ~ETR3_CF9GR); }
static void rcba_config(void) @@ -187,8 +187,8 @@ pch_enable_lpc();
/* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); outl (0x796bd9c3, DEFAULT_GPIOBASE); outl (0x86fec7c2, DEFAULT_GPIOBASE + 4); outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc); @@ -243,8 +243,8 @@ write_acpi16(0x0, 0x900); write_acpi32(0x20, 0xffff7ffe); write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); + pci_write_config8(LPC_DEV, GEN_PMCON_3, + pci_read_config8(LPC_DEV, GEN_PMCON_3) | 2); }
early_thermal_init(); diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index c7de994..6b017c0 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -24,7 +24,7 @@ { /* Enable KBC on 0x60/0x64 (KBC), EC on 0x62/0x66 (MC) */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); }
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index ca705a4..4b53d1f 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -26,11 +26,11 @@ void pch_enable_lpc(void) { /* COMA on 0x3f8, COMB on 0x2f8 */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable KBC on 0x60/0x64 (KBC), EC on 0x62/0x66 (MC), SIO on 0x2e/0x2f (CNF1) */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 4d5b667..3c3b8f9 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -41,20 +41,20 @@ void pch_enable_lpc(void) { /* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
/* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
try_enabling_LPC47N207_uart(); #else /* Enable SuperIO + EC + KBC */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); #endif } diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index bb11761..27b400b 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -55,20 +55,20 @@ void pch_enable_lpc(void) { /* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
/* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
try_enabling_LPC47N207_uart(); #else /* Enable SuperIO + PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); #endif }
diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c index 39bbc09..c2189b4 100644 --- a/src/northbridge/intel/fsp_sandybridge/report_platform.c +++ b/src/northbridge/intel/fsp_sandybridge/report_platform.c @@ -91,7 +91,7 @@ static void report_pch_info(void) { int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); + u16 dev_id = pci_read_config16(LPC_DEV, 2);
const char *pch_type = "Unknown"; @@ -102,7 +102,7 @@ } } printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); + pch_type, dev_id, pci_read_config8(LPC_DEV, 8)); }
void report_platform_info(void) diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 5b73844..f44b659 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -90,7 +90,7 @@ static void report_pch_info(void) { int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); + u16 dev_id = pci_read_config16(LPC_DEV, 2);
const char *pch_type = "Unknown"; @@ -101,7 +101,7 @@ } } printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); + pch_type, dev_id, pci_read_config8(LPC_DEV, 8)); }
void report_platform_info(void) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 490fd09..9268845 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -45,7 +45,7 @@ #include <delay.h>
#define NORTHBRIDGE PCI_DEV(0, 0, 0) -#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define GMA PCI_DEV (0, 0x2, 0x0) #define HECIDEV PCI_DEV(0, 0x16, 0) #define HECIBAR 0x10 @@ -3774,7 +3774,7 @@ timestamp_add_now(101);
if (!s3resume || 1) { // possible error - pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80 + pci_read_config8(LPC_DEV, GEN_PMCON_2); // = 0x80
collect_system_info(&info);
@@ -3893,7 +3893,7 @@ #endif
if (!s3resume) { - u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); + u8 reg8 = pci_read_config8(LPC_DEV, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) { /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); @@ -3902,7 +3902,7 @@
/* Clear bit7. */
- pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, + pci_write_config8(LPC_DEV, GEN_PMCON_2, (reg8 & ~(1 << 7)));
printk(BIOS_INFO, @@ -3913,8 +3913,8 @@ }
if (!s3resume && x2ca8 == 0) - pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); + pci_write_config8(LPC_DEV, GEN_PMCON_2, + pci_read_config8(LPC_DEV, GEN_PMCON_2) | 0x80);
compute_derived_timings(&info);
@@ -4767,8 +4767,8 @@ MCHBAR16_AND(0x1190, ~0x4000); }
- pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); + pci_write_config8(LPC_DEV, GEN_PMCON_2, + pci_read_config8(LPC_DEV, GEN_PMCON_2) & ~0x80); udelay(10000); MCHBAR16(0x2ca8) = 0x8;
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 7b4b3be..8ad7c4f 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -30,10 +30,10 @@ { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
- pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ + pci_write_config32(LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 46d5de8..7c4682a 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -306,7 +306,7 @@ wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 - if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ + if ((pci_read_config16(LPC_DEV, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ && reg_5d10 && !s3resume) { MCHBAR32(0x5d10) = 0; /* Need reset. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 317071c..2ff0142 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -133,7 +133,7 @@ dimm_info info; } ramctr_timing;
-#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define NORTHBRIDGE PCI_DEV(0, 0x0, 0) #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 63108de..84f8728 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -37,9 +37,9 @@ u8 reg8;
// reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); + reg8 = pci_read_config8(LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); + pci_write_config8(LPC_DEV, GEN_PMCON_3, reg8); }
/* Platform has no romstage entry point under mainboard directory, @@ -63,8 +63,8 @@ pch_enable_lpc();
/* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 865cf71..52fdc3a 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -194,7 +194,7 @@ #define LPC_FUNC 3 #define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) -#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) +#define LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
/* SD Controller */ #define SD_DEV 0x14 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 6833db6..5121cfa 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -275,7 +275,7 @@ wideio_index = sb_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(SOC_LPC_DEV, + *reg_x = pci_read_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
printk(BIOS_DEBUG, diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 763ddd7..d54f9e8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -197,9 +197,9 @@
if (index >= TOTAL_WIDEIO_PORTS) return size; - enable_register = pci_read_config32(SOC_LPC_DEV, + enable_register = pci_read_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); - alternate_register = pci_read_config8(SOC_LPC_DEV, + alternate_register = pci_read_config8(LPC_DEV, LPC_ALT_WIDEIO_RANGE_ENABLE); if (enable_register & wio_io_en[index].enable) size = (alternate_register & wio_io_en[index].alt) ? @@ -222,13 +222,13 @@ uint16_t end, current_size, start_wideio, end_wideio;
end = start + size; - enable_register = pci_read_config32(SOC_LPC_DEV, + enable_register = pci_read_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { current_size = sb_wideio_size(i); if (current_size == 0) continue; - start_wideio = pci_read_config16(SOC_LPC_DEV, + start_wideio = pci_read_config16(LPC_DEV, wio_io_en[i].port); end_wideio = start_wideio + current_size; if ((start >= start_wideio) && (end <= end_wideio)) { @@ -253,23 +253,23 @@ uint32_t enable_register; uint8_t alternate_register;
- enable_register = pci_read_config32(SOC_LPC_DEV, + enable_register = pci_read_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); - alternate_register = pci_read_config8(SOC_LPC_DEV, + alternate_register = pci_read_config8(LPC_DEV, LPC_ALT_WIDEIO_RANGE_ENABLE); for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { if (enable_register & wio_io_en[i].enable) continue; index = i; - pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start); + pci_write_config16(LPC_DEV, wio_io_en[i].port, start); enable_register |= wio_io_en[i].enable; - pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, + pci_write_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, enable_register); if (size <= 16) alternate_register |= wio_io_en[i].alt; else alternate_register &= ~wio_io_en[i].alt; - pci_write_config8(SOC_LPC_DEV, + pci_write_config8(LPC_DEV, LPC_ALT_WIDEIO_RANGE_ENABLE, alternate_register); break; @@ -322,9 +322,9 @@ { u8 byte;
- byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte = pci_read_config8(LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + pci_write_config8(LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); }
void sb_lpc_port80(void) @@ -339,9 +339,9 @@ outb(byte, PM_DATA);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ - byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte = pci_read_config8(LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + pci_write_config8(LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); }
void sb_lpc_decode(void) @@ -362,7 +362,7 @@ | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT | DECODE_ENABLE_ADLIB_PORT;
- pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); + pci_write_config32(LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); }
void sb_acpi_mmio_decode(void) @@ -413,13 +413,13 @@ u32 base, enables;
/* Make sure the base address is predictable */ - base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = pci_read_config32(LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); enables = base & 0xf; base &= ~0x3f;
if (!base) { base = SPI_BASE_ADDRESS; - pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, + pci_write_config32(LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, base | enables | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } @@ -468,9 +468,9 @@ { u32 value;
- value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE); + value = pci_read_config32(LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE); value |= TPM_12_EN | TPM_LEGACY_EN; - pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); + pci_write_config32(LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); }
/* @@ -485,9 +485,9 @@ sb_tpm_decode();
/* Route TPM accesses to SPI */ - u32 spibase = pci_read_config32(SOC_LPC_DEV, + u32 spibase = pci_read_config32(LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); - pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase + pci_write_config32(LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); }
@@ -508,18 +508,18 @@ * Decode variable LPC ROM address ranges 1 and 2. * Bits 3-4 are not defined in any publicly available datasheet */ - reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + reg8 = pci_read_config8(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); + pci_write_config8(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
/* * LPC ROM address range 1: * Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); + pci_write_config16(LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); + pci_write_config16(LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f);
/* * LPC ROM address range 2: @@ -530,11 +530,11 @@ * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 + pci_write_config16(LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); + pci_write_config16(LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); }
static void sb_lpc_early_setup(void) @@ -542,16 +542,16 @@ uint32_t dword;
/* Enable SPI prefetch */ - dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + dword = pci_read_config32(LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; - pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); + pci_write_config32(LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
if (IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)) { /* Decode SIOs at 2E/2F and 4E/4F */ - dword = pci_read_config32(SOC_LPC_DEV, + dword = pci_read_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - pci_write_config32(SOC_LPC_DEV, + pci_write_config32(LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, dword); } } diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 9baf433..b3880dd 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -112,7 +112,7 @@ { uintptr_t bar;
- bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); + bar = pci_read_config32(LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); bar = ALIGN_DOWN(bar, 64); set_spibar(bar); } diff --git a/src/soc/intel/denverton_ns/include/soc/lpc.h b/src/soc/intel/denverton_ns/include/soc/lpc.h index b1b4462..e661244 100644 --- a/src/soc/intel/denverton_ns/include/soc/lpc.h +++ b/src/soc/intel/denverton_ns/include/soc/lpc.h @@ -20,7 +20,7 @@ #define _DENVERTON_NS_LPC_H_
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, LPC_DEV, LPC_FUNC) +#define LPC_DEV PCI_DEV(0, LPC_DEV, LPC_FUNC)
#define SERIRQ_CNTL 0x64 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 97c8d5b..d88fc04 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -177,7 +177,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = dev_find_slot(FADT_SOC_LPC_DEV); + struct device *lpcdev = dev_find_slot(FADT_LPC_DEV); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = lpcdev->chip_info;
diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 832fb31..889e4e4c 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,7 +17,7 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_
-#define FADT_SOC_LPC_DEV 0, PCI_DEVFN(0x1f,0) +#define FADT_LPC_DEV 0, PCI_DEVFN(0x1f, 0)
/* PCI config registers in LPC bridge. */ #define REVID 0x08 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 8541903..023fd9f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -34,7 +34,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); @@ -44,7 +44,7 @@
static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
/* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index bda139b..32429f9 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -106,7 +106,7 @@
static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + u32 etr3 = pci_read_config32(LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -117,7 +117,7 @@ else etr3 &= ~ETR3_CF9GR;
- pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(LPC_DEV, ETR3, etr3); }
int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index a6562c7..3497367 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -112,7 +112,7 @@
static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + u32 etr3 = pci_read_config32(LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -123,7 +123,7 @@ else etr3 &= ~ETR3_CF9GR;
- pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(LPC_DEV, ETR3, etr3); }
int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 1254a16..16650f2 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -27,7 +27,7 @@ /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h>
-#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0)
static void wait_iobp(void) @@ -288,8 +288,8 @@ void early_pch_init_native (void) { - pci_write_config8 (SOUTHBRIDGE, 0xa6, - pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8(LPC_DEV, 0xa6, + pci_read_config8(LPC_DEV, 0xa6) | 2);
write32 (DEFAULT_RCBA + 0x2088, 0x00109000); read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index a08535e..9ef4369 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -55,13 +55,13 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4); + pci_or_config16(LPC_DEV, GEN_PMCON_1, 1 << 4);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); + pci_or_config8(LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
/* ETR3: CF9GR Lockdown */ - pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); + pci_update_config32(LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
/* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 66f5727..c70faf4 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -130,7 +130,7 @@ #define PCH_HPET_PCI_SLOT 15
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8..aeaed23 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -29,23 +29,23 @@
/* PCI Configuration Space (D31:F0): LPC */ #if defined(__SIMPLE_DEVICE__) -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) #endif
static u16 get_gpio_base(void) { #if defined(__SMM__) /* Don't assume GPIO_BASE is still the same */ - return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; + return pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffe; #else static u16 gpiobase CAR_GLOBAL;
if (gpiobase) return gpiobase;
- gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; + gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffe;
return gpiobase; #endif diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 360b63d..ed10711 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -28,23 +28,23 @@
/* PCI Configuration Space (D31:F0): LPC */ #if defined(__SIMPLE_DEVICE__) -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) #endif
u16 lpc_get_pmbase(void) { #if defined(__SMM__) /* Don't assume PMBASE is still the same */ - return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; + return pci_read_config16(LPC_DEV, PMBASE) & 0xfffc; #else static u16 pmbase CAR_GLOBAL;
if (pmbase) return pmbase;
- pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; + pmbase = pci_read_config16(LPC_DEV, PMBASE) & 0xfffc;
return pmbase; #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index f9f3134..3fb6724 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -180,7 +180,7 @@ u8 reg8;
// reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); } diff --git a/src/southbridge/intel/fsp_bd82x6x/early_me.c b/src/southbridge/intel/fsp_bd82x6x/early_me.c index 8faab62..540e3ce 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_me.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_me.c @@ -105,7 +105,7 @@
static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + u32 etr3 = pci_read_config32(LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -116,7 +116,7 @@ else etr3 &= ~ETR3_CF9GR;
- pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(LPC_DEV, ETR3, etr3); }
int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index af2f4e1..4287690 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -46,10 +46,10 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.c b/src/southbridge/intel/fsp_bd82x6x/gpio.c index b9e6c64..8c86bd9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/gpio.c +++ b/src/southbridge/intel/fsp_bd82x6x/gpio.c @@ -26,7 +26,7 @@
void setup_pch_gpios(const struct pch_gpio_map *gpio) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc;
/* GPIO Set 1 */ if (gpio->set1.level) @@ -65,7 +65,7 @@
int get_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; int index, bit;
if (gpio_num > MAX_GPIO_NUMBER) @@ -79,7 +79,7 @@
void set_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; u32 index, bit, level;
if (gpio_num <= MAX_GPIO_NUMBER){ @@ -96,7 +96,7 @@ } void clear_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; u32 index, bit, level;
if (gpio_num <= MAX_GPIO_NUMBER){ diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 1f1c18a..ec91423 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -116,7 +116,7 @@ #define PCH_PCIE_DEV_SLOT 28
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c index 7ce3c7f..7d9cdb1 100644 --- a/src/southbridge/intel/fsp_i89xx/early_init.c +++ b/src/southbridge/intel/fsp_i89xx/early_init.c @@ -67,7 +67,7 @@ u8 reg8;
// reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); } diff --git a/src/southbridge/intel/fsp_i89xx/early_me.c b/src/southbridge/intel/fsp_i89xx/early_me.c index 8faab62..540e3ce 100644 --- a/src/southbridge/intel/fsp_i89xx/early_me.c +++ b/src/southbridge/intel/fsp_i89xx/early_me.c @@ -105,7 +105,7 @@
static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + u32 etr3 = pci_read_config32(LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -116,7 +116,7 @@ else etr3 &= ~ETR3_CF9GR;
- pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(LPC_DEV, ETR3, etr3); }
int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index af2f4e1..4287690 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -46,10 +46,10 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/fsp_i89xx/gpio.c b/src/southbridge/intel/fsp_i89xx/gpio.c index b9e6c64..8c86bd9 100644 --- a/src/southbridge/intel/fsp_i89xx/gpio.c +++ b/src/southbridge/intel/fsp_i89xx/gpio.c @@ -26,7 +26,7 @@
void setup_pch_gpios(const struct pch_gpio_map *gpio) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc;
/* GPIO Set 1 */ if (gpio->set1.level) @@ -65,7 +65,7 @@
int get_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; int index, bit;
if (gpio_num > MAX_GPIO_NUMBER) @@ -79,7 +79,7 @@
void set_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; u32 index, bit, level;
if (gpio_num <= MAX_GPIO_NUMBER){ @@ -96,7 +96,7 @@ } void clear_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; u32 index, bit, level;
if (gpio_num <= MAX_GPIO_NUMBER){ diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 3382cbd..290f747 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -102,7 +102,7 @@ #define PCH_PCIE_DEV_SLOT 28
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index afe00bd..274a0e3 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -50,7 +50,7 @@
static void pch_enable_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; + pci_devfn_t dev = LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); @@ -105,8 +105,8 @@ pch_enable_lpc();
/* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
/* Call into mainboard. */ early_mainboard_romstage_entry(); diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index ca711dc..844368b 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -34,7 +34,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = dev_find_slot(SOC_LPC_DEVFN); + struct device *lpcdev = dev_find_slot(LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = lpcdev->chip_info;
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 0a287c4..ce9f7aa 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -25,8 +25,8 @@
void setup_soc_gpios(const struct soc_gpio_map *gpio) { - u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf; - u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf); + u16 gpiobase = pci_read_config16(LPC_DEV, GBASE) & ~0xf; + u32 *cfiobase = (u32 *)(pci_read_config32(LPC_DEV, IOBASE) & ~0xf); u32 cfio_cnt = 0;
@@ -92,7 +92,7 @@
int get_gpio(int gpio_num) { - u16 gpio_base = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf; + u16 gpio_base = pci_read_config16(LPC_DEV, GBASE) & ~0xf; int bit;
if (gpio_num > MAX_GPIO_NUMBER) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2f598d8..b1730a1 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -57,7 +57,7 @@ post_code(0x41);
/* Enable GPIOs BAR */ - pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02); + pci_write_config32(LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02);
early_mainboard_romstage_entry();
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0917201..60594da 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -92,8 +92,8 @@ #define PCIE_DEV_SLOT3 4
/* PCI Configuration Space (D31:F0): LPC */ -#define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0) -#define SOC_LPC_DEVFN 0, PCI_DEVFN(0x1f,0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEVFN 0, PCI_DEVFN(0x1f, 0)
/* Southbridge IO BARs */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 55478b9..364f33e 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -107,7 +107,7 @@ #define PCH_PCIE_DEV_SLOT 28
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 674534f..f18e64b 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -106,7 +106,7 @@
static inline void set_global_reset(int enable) { - u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR); + u32 pmir = pci_read_config32(LPC_DEV, PMIR);
/* CF9GR indicates a Global Reset */ if (enable) @@ -114,7 +114,7 @@ else pmir &= ~PMIR_CF9GR;
- pci_write_config32(PCH_LPC_DEV, PMIR, pmir); + pci_write_config32(LPC_DEV, PMIR, pmir); }
int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 4c45613..ed1e9bf 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -41,23 +41,23 @@
int pch_is_lp(void) { - u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + u8 id = pci_read_config8(LPC_DEV, PCI_DEVICE_ID + 1); return id == PCH_TYPE_LPT_LP; }
static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
- pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(LPC_DEV, ACPI_CNTL, 0x80);
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
/* Enable GPIO functionality. */ - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); }
static void pch_generic_setup(void) @@ -103,12 +103,12 @@ const struct southbridge_intel_lynxpoint_config *config = NULL;
/* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + pci_write_config16(LPC_DEV, LPC_EN, lpc_config);
/* Set up generic decode ranges */ if (!dev) @@ -118,10 +118,10 @@ if (!config) return;
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); }
int early_pch_init(const void *gpio_map, diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 590a245..fdda146 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -50,10 +50,10 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* PMSYNC */ RCBA32_OR(PMSYNC_CONFIG, (1UL << 31)); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2b07de2..3a40df2 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -25,7 +25,7 @@ static u16 get_gpio_base(void) { #if defined(__PRE_RAM__) || defined(__SMM__) - return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + return pci_read_config16(LPC_DEV, GPIO_BASE) & 0xfffc; #else return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & 0xfffc; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ae996e8..912cee1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -238,7 +238,7 @@ #define PCH_PCIE_DEV_SLOT 28
/* PCI Configuration Space (D31:F0): LPC */ -#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0