Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22940

Change subject: google/kahlee: Create mainboard_pirq_data
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google/kahlee: Create mainboard_pirq_data

When booting kahlee, there's an error message: "Warning: Can't write PCI
IRQ assignments because 'mainboard_pirq_data' structure does not exist".
This is caused by missing mainboard_pirq_data.

Create mainboard_pirq_data and update pirq_setup() to set the values of
pirq_data_ptr and pirq_data_size.

BUG=b:70788755
TEST=Build and boot kahlee. Warning message must be gone. Verify output
from write_pci_cfg_irqs and explain anything that does not fit a pattern
(what all other devices are producing).

Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a
Signed-off-by: Richard Spiegel 
---
M src/mainboard/google/kahlee/mainboard.c
1 file changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22940/1

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 0954a29..6deac3f 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -22,6 +22,7 @@
 #include <baseboard/variants.h>
 #include <boardid.h>
 #include <soc/nvs.h>
+#include <soc/pci_devs.h>
 #include <soc/smi.h>
 #include <soc/southbridge.h>
 #include <variant/ec.h>
@@ -77,9 +78,36 @@
    [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };

+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device.  Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01.  This index will define
+ * the interrupt that it should use.  Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+	{PCIE0_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe 0 */
+	{PCIE1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe 1 */
+	{PCIE2_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe 2 */
+	{PCIE3_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe 3 */
+	{PCIE4_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe 4 */
+	{HDA0_DEVFN,	{PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC} }, /* HDA */
+	{SD_DEVFN,	{PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* SD */
+	{SMBUS_DEVFN,	{PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SMBUS */
+	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA */
+	{EHCI1_DEVFN,	{PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* EHCI */
+	{XHCI_DEVFN,	{PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* XHCI */
+};
+
 /* PIRQ Setup */
 static void pirq_setup(void)
 {
+	pirq_data_ptr = mainboard_pirq_data;
+	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
    intr_data_ptr = mainboard_intr_data;
    picr_data_ptr = mainboard_picr_data;
 }