Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52905
to look at the new patch set (#2).
Change subject: [UNTESTED] soc/amd/cezanne: add GNB IOAPIC support ......................................................................
[UNTESTED] soc/amd/cezanne: add GNB IOAPIC support
To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address.
BUG=b:187083211
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/root_complex.c 4 files changed, 29 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52905/2