Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings - coreboot-gerrit

7 May 2021


      Attention is currently required from: Angel Pons, Patrick Rudolph.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52815 )
Change subject: aopen/dxplplusu: Add early GPIO settings
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Patch Set 1:
(1 comment)
File src/mainboard/aopen/dxplplusu/bootblock.c:
https://review.coreboot.org/c/coreboot/+/52815/comment/a1f3b77a_44dffc45 
PS1, Line 13: #define PME_BASE 0xe00
...
Shouldn't this be reserved in the allocator?
Do we account for PNP fixed IO's in read_resources? This does fall into into the 0x0-0x1000 IO region the southbridge reserves.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579
Gerrit-Change-Number: 52815
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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