[M] Change in coreboot[main]: soc/amd/common/block/lpc: Use ROM3 window if possible

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Maximilian Brune, Patrick Rudolph, Paul Menzel, Varshit Pandya.

Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86584?usp=email )

Change subject: soc/amd/common/block/lpc: Use ROM3 window if possible
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Patch Set 11:

(2 comments)

Patchset:

PS11: 
haven't gotten around to do a proper review, but wanted to at least roughly document here what we discussed today

File src/soc/amd/common/block/spi/mmap_boot_rom3.c:

https://review.coreboot.org/c/coreboot/+/86584/comment/032c56a5_f936d690?usp... :
PS11, Line 62:  *             0   +------------+ ------------------------------0xFF0000000--+--------------+- rom2_start
> Document 56780 describes the remapping for ROM3 as well. […]

coreboot makes assumptions that it's in the lowest 16mbyte and that that also contains the efs
as discussed via chat, i'm ok with using therom2 mapping for the first 16mbytes and rom3 for the rest for now we should make sure though that there's no remapping going on and the 16mbytes of the spi flash mapped right below 4gb as rom2 are actually the first 16mbytes