Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60123 )
Change subject: mb/starlabs/labtop: Tidy up GPIOs ......................................................................
mb/starlabs/labtop: Tidy up GPIOs
Add label to GPIO and categorise per device
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a --- M src/mainboard/starlabs/labtop/variants/tgl/gpio.c 1 file changed, 395 insertions(+), 196 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/60123/1
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c index a541c07..b48bc28 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -9,8 +9,11 @@
/* Early pad configuration in romstage. */ const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* + * UART 2: Debug + */ + /* RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), };
const struct pad_config *variant_early_gpio_table(size_t *num) @@ -21,200 +24,396 @@
/* Pad configuration in ramstage.c */ const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), - PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), - PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD7, 0, PWROK), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_CFG_NF(GPD9, NONE, PWROK, NF1), - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD11, 0, PWROK), - PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_NC(GPP_A7, NONE), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), - PAD_NC(GPP_A10, NONE), - PAD_CFG_GPO(GPP_A11, 1, PLTRST), - PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), - PAD_NC(GPP_A13, NONE), - PAD_CFG_GPO(GPP_A14, 0, PLTRST), - PAD_NC(GPP_A15, NONE), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - PAD_NC(GPP_A19, NONE), - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_CFG_GPO(GPP_A23, 0, PLTRST), - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_CFG_GPO(GPP_B17, 0, PWROK), - PAD_CFG_GPO(GPP_B18, 0, DEEP), - PAD_NC(GPP_B19, NONE), - PAD_NC(GPP_B20, NONE), - PAD_NC(GPP_B21, NONE), - PAD_CFG_GPO(GPP_B22, 0, DEEP), - PAD_CFG_GPO(GPP_B23, 0, DEEP), - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C2, 0, DEEP), - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C5, 0, DEEP), - PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - PAD_NC(GPP_C9, NONE), - PAD_CFG_GPO(GPP_C10, 0, PWROK), - PAD_CFG_GPO(GPP_C11, 0, PWROK), - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_C13, 1, PLTRST), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - PAD_NC(GPP_C22, NONE), - PAD_NC(GPP_C23, NONE), - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_CFG_GPI(GPP_D2, NONE, DEEP), - PAD_CFG_GPI(GPP_D3, NONE, DEEP), - PAD_NC(GPP_D4, NONE), - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_NC(GPP_D9, NATIVE), - PAD_NC(GPP_D10, NATIVE), - PAD_NC(GPP_D11, NATIVE), - PAD_NC(GPP_D12, NATIVE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_CFG_GPO(GPP_D16, 1, PLTRST), - PAD_CFG_GPI(GPP_D17, NONE, DEEP), - PAD_CFG_GPI(GPP_D18, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_NC(GPP_E6, NONE), - PAD_NC(GPP_E7, NONE), - PAD_NC(GPP_E8, NONE), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_NC(GPP_E10, NONE), - PAD_NC(GPP_E11, NONE), - PAD_NC(GPP_E12, NONE), - PAD_NC(GPP_E13, NONE), - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), - PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NATIVE), - PAD_NC(GPP_E19, NATIVE), - PAD_NC(GPP_E20, NATIVE), - PAD_NC(GPP_E21, NATIVE), - PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2), - PAD_CFG_GPO(GPP_E23, 0, DEEP), - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), - PAD_NC(GPP_F6, NONE), - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - PAD_NC(GPP_F8, NONE), - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - PAD_CFG_GPO(GPP_F10, 0, DEEP), - PAD_NC(GPP_F11, NONE), - PAD_NC(GPP_F12, NONE), - PAD_NC(GPP_F13, NONE), - PAD_NC(GPP_F14, NONE), - PAD_NC(GPP_F15, NONE), - PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - PAD_NC(GPP_F22, NONE), - PAD_NC(GPP_F23, NONE), - PAD_CFG_GPO(GPP_H0, 0, DEEP), - PAD_CFG_GPO(GPP_H1, 0, DEEP), - PAD_CFG_GPO(GPP_H2, 0, DEEP), - PAD_NC(GPP_H3, NONE), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - PAD_NC(GPP_H10, NONE), - PAD_NC(GPP_H11, NONE), - PAD_NC(GPP_H12, NONE), - PAD_NC(GPP_H13, NONE), - PAD_CFG_GPO(GPP_H14, 1, PLTRST), - PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - PAD_CFG_GPO(GPP_H23, 0, DEEP), - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_R5, 0, PLTRST), - PAD_CFG_GPO(GPP_R6, 1, PLTRST), - PAD_NC(GPP_R7, NONE), - PAD_NC(GPP_S0, NONE), - PAD_NC(GPP_S1, NONE), - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), - PAD_NC(GPP_S4, NONE), - PAD_NC(GPP_S5, NONE), - PAD_NC(GPP_S6, NONE), - PAD_NC(GPP_S7, NONE), - PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), - PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), - PAD_NC(GPP_U4, NONE), - PAD_NC(GPP_U5, NONE), + /* BATLOW */ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* LAN WAKE */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + /* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* S3 */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* S4 */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* A */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD 7 */ PAD_CFG_GPO(GPD7, 0, PWROK), + /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* WLAN */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* S5 */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* LANPHYPC */ PAD_CFG_GPO(GPD11, 0, PWROK), + + /* + * ESPI + */ + /* IO 0 */ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* IO 1 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* IO 2 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* IO 3 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* CS */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* CLK */ PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + /* RESET */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* + * Power Managent Controller + */ + /* ALERT */ PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + + /* SLP S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* + * GSPI 0: ? + */ + /* CS0 */ PAD_NC(GPP_B15, NONE), + /* CLK */ PAD_NC(GPP_B16, NONE), + /* MISO */ PAD_CFG_GPO(GPP_B17, 0, PWROK), + /* MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), + + /* + * GSPI 1: ? + */ + /* CS0 */ PAD_NC(GPP_B19, NONE), + /* CLK */ PAD_NC(GPP_B20, NONE), + /* MISO */ PAD_NC(GPP_B21, NONE), + /* MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), + + /* + * SMBus + */ + /* CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_C2, 0, DEEP), + + /* + * SML 0 + */ + /* CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_C5, 0, DEEP), + + /* + * SML 1 + */ + /* CLK */ PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), + /* DATA */ PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), + /* ALERT */ PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* + * VR + */ + /* ALERT */ PAD_NC(GPP_B2, NONE), + + /* + * CNV + */ + /* BRI DT */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* BRI RSP */ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* RGI DT */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* RGI FSP */ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* RF RESET */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* MODEL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* PA BLANK */ PAD_NC(GPP_F6, NONE), + + /* + * UART 0: Trackpad + */ + /* RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* TXD */ PAD_NC(GPP_C9, NONE), + /* RTS */ PAD_CFG_GPO(GPP_C10, 0, PWROK), + /* CTS */ PAD_CFG_GPO(GPP_C11, 0, PWROK), + + /* + * UART 1: Integrated Sensor Hub + */ + /* RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* TXD */ PAD_CFG_GPO(GPP_C13, 1, PLTRST), + /* RTS */ PAD_NC(GPP_C14, NONE), + /* CTS */ PAD_NC(GPP_C15, NONE), + + /* + * I2C 0 + */ + /* SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* + * I2C 1 + */ + /* SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* + * UART 2: Debug + */ + /* RTS */ PAD_NC(GPP_C22, NONE), + /* CTS */ PAD_NC(GPP_C23, NONE), + + /* + * Integrated Sensor Hub + */ + /* GP 0 */ PAD_NC(GPP_D0, NONE), + /* GP 1 */ PAD_NC(GPP_D1, NONE), + /* GP 2 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* GP 3 */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* GP 4 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), + /* GP 5 */ PAD_CFG_GPI(GPP_D18, NONE, DEEP), + /* GP 6 */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), + /* GP 7 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + + /* CS */ PAD_NC(GPP_D9, NATIVE), + /* CLK */ PAD_NC(GPP_D10, NATIVE), + /* MISO */ PAD_NC(GPP_D11, NATIVE), + /* MOSI */ PAD_NC(GPP_D12, NATIVE), + + /* RXD */ PAD_NC(GPP_D13, NONE), + /* TXD */ PAD_NC(GPP_D14, NONE), + /* RTS */ PAD_NC(GPP_D15, NONE), + /* CTS */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* + * ISH I2C 0 + */ + /* SDA */ PAD_NC(GPP_B5, NONE), + /* SCL */ PAD_NC(GPP_B6, NONE), + + /* + * ISH I2C 1 + */ + /* SDA */ PAD_NC(GPP_B7, NONE), + /* SCL */ PAD_NC(GPP_B8, NONE), + + /* + * ISH I2C 2 + */ + /* SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + /* + * Clock Request + */ + /* REQ 0 */ PAD_NC(GPP_D5, NONE), + /* REQ 1 */ PAD_NC(GPP_D6, NONE), + /* REQ 2 */ PAD_NC(GPP_D7, NONE), + /* REQ 3 */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* REQ 4 */ PAD_NC(GPP_H10, NONE), + /* REQ 5 */ PAD_NC(GPP_H11, NONE), + /* REQ 6 */ PAD_NC(GPP_F19, NONE), + + /* + * SATA + */ + /* GP 0 */ PAD_NC(GPP_E0, NONE), + /* LED */ PAD_NC(GPP_E8, NONE), + + /* + * Dev + */ + /* SLP 0 */ PAD_NC(GPP_E4, NONE), + /* SLP 1 */ PAD_NC(GPP_E5, NONE), + + /* + * THC 0 + */ + /* RST */ PAD_NC(GPP_E6, NONE), + /* INT */ PAD_NC(GPP_E17, NONE), + /* SPI 1 CS */ PAD_NC(GPP_E10, NONE), + /* SPI 1 CLK */ PAD_NC(GPP_E11, NONE), + /* SPI 1 IO0 */ PAD_NC(GPP_E13, NONE), + /* SPI 1 IO1 */ PAD_NC(GPP_E12, NONE), + /* SPI 1 IO2 */ PAD_NC(GPP_E1, NONE), + /* SPI 1 IO3 */ PAD_NC(GPP_E2, NONE), + + /* + * THC 1 + */ + /* RST */ PAD_NC(GPP_F17, NONE), + /* INT */ PAD_NC(GPP_F18, NONE), + /* SPI 2 CS */ PAD_NC(GPP_F16, NONE), + /* SPI 2 CLK */ PAD_NC(GPP_F11, NONE), + /* SPI 2 IO0 */ PAD_NC(GPP_F12, NONE), + /* SPI 2 IO1 */ PAD_NC(GPP_F13, NONE), + /* SPI 2 IO2 */ PAD_NC(GPP_F14, NONE), + /* SPI 2 IO3 */ PAD_NC(GPP_F15, NONE), + + /* + * USB + */ + /* OC 0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + /* OC 2 */ PAD_NC(GPP_A15, NONE), + /* OC 3 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* + * DISP + */ + /* MISCC */ PAD_NC(GPP_A17, NONE), + + /* + * DDSP + */ + /* HPDA */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* DPDB */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* HPD 1 */ PAD_NC(GPP_A19, NONE), + /* HPD 2 */ PAD_NC(GPP_A20, NONE), + + /* F7 */ PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* F9 */ PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10 */ PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* + * External Power + */ + /* GATE 1 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* GATE 2 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + + /* VNN CTRL */ PAD_NC(GPP_F22, NONE), + /* V1P05 */ PAD_NC(GPP_F23, NONE), + + /* H0 */ PAD_CFG_GPO(GPP_H0, 0, DEEP), + /* H1 */ PAD_CFG_GPO(GPP_H1, 0, DEEP), + /* H2 */ PAD_CFG_GPO(GPP_H2, 0, DEEP), + + /* + * I2C 2 + */ + /* SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* + * I2C 3 + */ + /* SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* + * I2C 4 + */ + /* SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* + * M2 SKT 2 + */ + /* CFG 0 */ PAD_NC(GPP_H12, NONE), + /* CFG 1 */ PAD_NC(GPP_H13, NONE), + /* CFG 2 */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* CFG 3 */ PAD_NC(GPP_H15, NONE), + + /* + * DDPA + */ + /* CTRL CLK */ PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2), + /* CTRL DATA */ PAD_CFG_GPO(GPP_E23, 0, DEEP), + + /* + * DDPB + */ + /* CTRL CLK */ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* CTRL DATA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* + * DDPC + */ + /* CTRL CLK */ PAD_NC(GPP_A21, NONE), + /* CTRL DATA */ PAD_NC(GPP_A22, NONE), + + /* DDP1 */ + /* CTRL CLK */ PAD_NC(GPP_E18, NATIVE), + /* CTRL DATA */ PAD_NC(GPP_E19, NATIVE), + + /* DDP2 */ + /* CTRL CLK */ PAD_NC(GPP_E20, NATIVE), + /* CTRL DATA */ PAD_NC(GPP_E21, NATIVE), + + /* + * CPU + */ + /* C10 GATE */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + /* GP1 */ PAD_NC(GPP_E7, NONE), + /* GP2 */ PAD_NC(GPP_B3, NONE), + /* GP3 */ PAD_NC(GPP_B4, NONE), + /* SX EXIT */ PAD_NC(GPP_H3, NONE), + /* VID 0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* VID 1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* + * Time + */ + /* SYNC 0 */ PAD_NC(GPP_H19, NONE), + /* SYNC 1 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* + * Image Clock + */ + /* OUT 0 */ PAD_NC(GPP_D4, NONE), + /* OUT 1 */ PAD_NC(GPP_H20, NONE), + /* OUT 2 */ PAD_NC(GPP_H21, NONE), + /* OUT 3 */ PAD_NC(GPP_H22, NONE), + /* OUT 4 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* + * I2S + */ + /* MCLK1 */ PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), + /* MCLK2 */ PAD_NC(GPP_F8, NONE), + + /* + * I2S 0 + */ + /* SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* SFRM */ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* TXD */ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* RXD */ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* RST */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* + * I2S 1 + */ + /* CLK */ PAD_CFG_GPO(GPP_A23, 0, PLTRST), + /* RXD */ PAD_CFG_GPO(GPP_R5, 0, PLTRST), + /* TXD */ PAD_CFG_GPO(GPP_R6, 1, PLTRST), + /* SFRM */ PAD_NC(GPP_R7, NONE), + + /* + * I2S 2 + */ + /* CLK */ PAD_NC(GPP_A7, NONE), + /* RXD */ PAD_NC(GPP_A10, NONE), + /* TXD */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), + /* SFRM */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + + /* + * I2S 3 + */ + /* CLK */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* RXD */ PAD_CFG_GPO(GPP_A14, 0, PLTRST), + /* TXD */ PAD_NC(GPP_A13, NONE), + /* SFRM */ PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* + * Soundwire 0 + */ + /* CLK */ PAD_NC(GPP_S0, NONE), + /* DATA */ PAD_NC(GPP_S1, NONE), + + /* + * Soundwire 1 + */ + /* CLK */ PAD_NC(GPP_S2, NONE), + /* DATA */ PAD_NC(GPP_S3, NONE), + + /* + * Soundwire 2 + */ + /* CLK */ PAD_NC(GPP_S4, NONE), + /* DATA */ PAD_NC(GPP_S5, NONE), + + /* + * Soundwire 3 + */ + /* CLK */ PAD_NC(GPP_S6, NONE), + /* DATA */ PAD_NC(GPP_S7, NONE), + + /* NOT USED */ PAD_NC(GPP_T2, NONE), + /* NOT USED */ PAD_NC(GPP_T3, NONE), + /* NOT USED */ PAD_NC(GPP_U4, NONE), + /* NOT USED */ PAD_NC(GPP_U5, NONE), };
const struct pad_config *variant_gpio_table(size_t *num)
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Sean Rhodes (Code Review)