[XS] Change in coreboot[main]: soc/intel/skylake: Change the maximum C state to C8

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86201?usp=email )

Change subject: soc/intel/skylake: Change the maximum C state to C8
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soc/intel/skylake: Change the maximum C state to C8

The EDS says that SkyLake "supports C0, C2, C3, C6, C8,
and C10 package states". Update the highest state for non-S0ix
boards accordingly.

Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86201
Reviewed-by: Jérémy Compostella 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Jérémy Compostella: Looks good to me, approved

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 3a60ada..7694033 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -124,7 +124,7 @@
 static int cstate_set_non_s0ix[] = {
    C_STATE_C1E,
    C_STATE_C3,
-	C_STATE_C7S_LONG_LAT,
+	C_STATE_C8
 };

const acpi_cstate_t *soc_get_cstate_map(size_t *entries)