[M] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

[Gareth Yu (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik.

Gareth Yu has uploaded a new patch set (#26) to the change originally created by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email )

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................

mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

According to the analysis results, resetting the DSI DPHY to default
during a warm boot is needed if 'You are in developer mode' needs to be
displayed on the screen in a system using the MIPI-DSI panel.

DPHY_0_CLOCK_LANE_TIMING -- address:0x162180, size: 32 bits
[31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides
[30..28]: CLK_PREPARE
[27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides
[23..20]: CLK_ZERO
[19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides
[17..16]: CLK_PRE
[15]: CLK_POST Override. 0:HW maintains, 1:SW overrides
[10..8]: CLK_POST
[7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides
[2..0]: CLK_TRAIL

BUG=b:397805262
TEST=Able to show 'You are in developer mode'

Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179
Signed-off-by: Gareth Yu 
---
M src/mainboard/google/brya/variants/meliks/Makefile.mk
A src/mainboard/google/brya/variants/meliks/ramstage.c
2 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86838/26