Change in coreboot[master]: mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hex

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54376 )

Change subject: mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hex
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mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hex

Done for consistency with the other variants.

Tested with BUILD_TIMELESS=1, Asus P8H61-M LX remains identical.

Change-Id: I440706f6fa11d3c2410c445cb7e946c063578c4e
Signed-off-by: Angel Pons 
---
M src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/54376/1

diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
index 2761190..05b8e38 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb
@@ -19,7 +19,7 @@
    	device pci 02.0 on end # VGA controller

chip southbridge/intel/bd82x6x
-			register "c2_latency" = "101"
+			register "c2_latency" = "0x0065"
    		register "gen1_dec" = "0x00000295" # Super I/O HWM
    		register "sata_port_map" = "0x33"
    		register "spi_lvscc" = "0x2005"