Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51439 )
Change subject: nb/intel/haswell: Move `pei_data` uses into raminit.c ......................................................................
nb/intel/haswell: Move `pei_data` uses into raminit.c
Change-Id: I1aa19d6ebb2f780835b3103c3527a5d91c3e9ff5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/romstage.c 3 files changed, 90 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/51439/1
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 58ac8a0..34d28dd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -16,6 +16,10 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> +#include <northbridge/intel/haswell/chip.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <timestamp.h> #include <types.h>
#include "raminit.h" @@ -105,7 +109,7 @@ * * @param pei_data: configuration data for UEFI PEI reference code */ -void sdram_initialize(struct pei_data *pei_data) +static void sdram_initialize(struct pei_data *pei_data) { int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1)));
@@ -167,6 +171,89 @@ report_memory_config(); }
+/* Copy SPD data for on-board memory */ +void __weak copy_spd(struct pei_data *peid) +{ +} + +/* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ +static int make_channel_disabled_mask(const struct pei_data *pd, int ch) +{ + return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); +} + +void perform_raminit(const int s3resume) +{ + const struct device *gbe = pcidev_on_root(0x19, 0); + + const struct northbridge_intel_haswell_config *cfg = config_of_soc(); + + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, + .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, + .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ec_present = cfg->ec_present, + .gbe_enable = gbe && gbe->enabled, + .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), + .dq_pins_interleaved = cfg->dq_pins_interleaved, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = cfg->usb_xhci_on_resume, + }; + + memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); + memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); + + /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ + pei_data.boot_mode = s3resume ? 2 : 0; + + /* Obtain the SPD addresses from mainboard code */ + mb_get_spd_map(pei_data.spd_addresses); + + /* Calculate unimplemented DIMM slots for each channel */ + pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); + pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); + + copy_spd(&pei_data); + + timestamp_add_now(TS_BEFORE_INITRAM); + + sdram_initialize(&pei_data); + + timestamp_add_now(TS_AFTER_INITRAM); + + post_code(0x3b); + + intel_early_me_status(); + + int cbmem_was_initted = !cbmem_recovery(s3resume); + if (s3resume && !cbmem_was_initted) { + /* Failed S3 resume, reset to come up cleanly */ + printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); + system_reset(); + } + + /* Save data returned from MRC on non-S3 resumes. */ + if (!s3resume) + save_mrc_data(&pei_data); + + setup_sdram_meminfo(&pei_data); +} + static uint8_t nb_get_ecc_type(const uint32_t capid0_a) { return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 6efea3e..2cfc4cf 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -16,7 +16,7 @@ /* Mainboard callback to fill in the SPD addresses in MRC format */ void mb_get_spd_map(uint8_t spd_map[4]);
-void sdram_initialize(struct pei_data *pei_data); +void perform_raminit(const int s3resume); void setup_sdram_meminfo(struct pei_data *pei_data);
/* save_mrc_data() must be called after cbmem has been initialized. */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 48ba476..c560241 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <elog.h> -#include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> #include <commonlib/helpers.h> @@ -14,66 +13,19 @@ #include <security/intel/txt/txt.h> #include <security/intel/txt/txt_register.h> #include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> #include <string.h>
-/* Copy SPD data for on-board memory */ -void __weak copy_spd(struct pei_data *peid) -{ -} - void __weak mb_late_romstage_setup(void) { }
-/* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ -static int make_channel_disabled_mask(const struct pei_data *pd, int ch) -{ - return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); -} - /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - const struct device *gbe = pcidev_on_root(0x19, 0); - - const struct northbridge_intel_haswell_config *cfg = config_of_soc(); - - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = get_pch_platform_type(), - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .ec_present = cfg->ec_present, - .gbe_enable = gbe && gbe->enabled, - .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), - .dq_pins_interleaved = cfg->dq_pins_interleaved, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = cfg->usb_xhci_on_resume, - }; - - memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); - memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); - enable_lapic();
early_pch_init(); @@ -94,28 +46,12 @@
post_code(0x3a);
- /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ - pei_data.boot_mode = s3resume ? 2 : 0; - - /* Obtain the SPD addresses from mainboard code */ - mb_get_spd_map(pei_data.spd_addresses); - - /* Calculate unimplemented DIMM slots for each channel */ - pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); - pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); - - timestamp_add_now(TS_BEFORE_INITRAM); - report_platform_info();
if (CONFIG(INTEL_TXT)) intel_txt_romstage_init();
- copy_spd(&pei_data); - - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); + perform_raminit(s3resume);
if (CONFIG(INTEL_TXT)) { printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); @@ -129,26 +65,8 @@ txt_dump_regions(); }
- post_code(0x3b); - - intel_early_me_status(); - - int cbmem_was_initted = !cbmem_recovery(s3resume); - if (s3resume && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); - system_reset(); - } - - /* Save data returned from MRC on non-S3 resumes. */ - if (!s3resume) - save_mrc_data(&pei_data); - - haswell_unhide_peg();
- setup_sdram_meminfo(&pei_data); - romstage_handoff_init(s3resume);
mb_late_romstage_setup();
-
Angel Pons (Code Review)