Change in coreboot[master]: coreboot:[TEST ONLY] Add support for boot with tianocore payload
Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload ......................................................................
coreboot:[TEST ONLY] Add support for boot with tianocore payload
Add FSP UPDs and set gbb flags through Kconfig required to boot with tianocore payload.
Change-Id: I42fcf23523889d47f0490fad662ca6b3587ab548 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35376/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index c4c9146..259827f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -21,6 +21,8 @@ select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SYSTEM_TYPE_LAPTOP + select GBB_FLAG_ENABLE_ALTERNATE_OS + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
if BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..1637765 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -56,7 +56,7 @@ # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77"
- register "PmTimerDisabled" = "1" + register "PmTimerDisabled" = "0"
# VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f48a626..dbaedb7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -249,6 +249,7 @@
/* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = 0; params->Enable8254ClockGatingOnS3 = 1;
/* USB */
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload ......................................................................
Patch Set 1:
This change is ready for review.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload ......................................................................
Patch Set 4:
This change is ready for review.
Meera Ravindranath has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload ......................................................................
Removed reviewer Patrick Rudolph.
Hello Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35376
to look at the new patch set (#5).
Change subject: coreboot:Add support for boot with tianocore payload ......................................................................
coreboot:Add support for boot with tianocore payload
Add FSP UPDs and set gbb flags through Kconfig required to boot with tianocore payload.
Change-Id: I42fcf23523889d47f0490fad662ca6b3587ab548 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/common/block/timer/Kconfig 3 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35376/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:Add support for boot with tianocore payload ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/35376/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35376/5//COMMIT_MSG@7 PS5, Line 7: coreboot:Add Better summary required
https://review.coreboot.org/c/coreboot/+/35376/5//COMMIT_MSG@9 PS5, Line 9: FSP Not true, works without this commit on at least one board.
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... PS5, Line 59: PmTimerDisabled Should be set in SoC/Intel/ No need to make it mainboard specific.
https://review.coreboot.org/c/coreboot/+/35376/5/src/soc/intel/common/block/... File src/soc/intel/common/block/timer/Kconfig:
https://review.coreboot.org/c/coreboot/+/35376/5/src/soc/intel/common/block/... PS5, Line 16: USE_PM_TIMER_DISABLED Inverse: USE_PM_TIMER
https://review.coreboot.org/c/coreboot/+/35376/5/src/soc/intel/common/block/... PS5, Line 20: PM What's a PM timer?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:Add support for boot with tianocore payload ......................................................................
Patch Set 5:
(1 comment)
Welcome to coreboot. Please join #coreboot@irc.freenode.net or contact the mailing list in case of questions.
https://review.coreboot.org/c/coreboot/+/35376/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35376/5//COMMIT_MSG@7 PS5, Line 7: coreboot:Add
Better summary required
… including a better prefix. Please see `git log --oneline`. Please split the board and soc commit into separate commits.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:Add support for boot with tianocore payload ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/Kconfig:
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... PS5, Line 44: select USE_LEGACY_8254_TIME can add select USE_PM_TIMER after you make change in config name.
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35376/5/src/mainboard/google/hatch/... PS5, Line 59: PmTimerDisabled
Should be set in SoC/Intel/ […]
Agree. you can move it to fsp_params.c directly and set it based on the Kconfig
https://review.coreboot.org/c/coreboot/+/35376/5/src/soc/intel/common/block/... File src/soc/intel/common/block/timer/Kconfig:
https://review.coreboot.org/c/coreboot/+/35376/5/src/soc/intel/common/block/... PS5, Line 16: USE_PM_TIMER_DISABLED
Inverse: USE_PM_TIMER
or USE_ACPI_PM_TIMER
Meera Ravindranath has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35376 )
Change subject: coreboot:Add support for boot with tianocore payload ......................................................................
Abandoned
Split the soc and mainboard changes and pushed three separate CLs. https://review.coreboot.org/c/coreboot/+/36034 https://review.coreboot.org/c/coreboot/+/36064 https://review.coreboot.org/c/coreboot/+/36067
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Aamir Bohra (Code Review) -
Meera Ravindranath (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)