Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Kapil Porwal, Arthur Heymans.
Hello build bot (Jenkins), Tarun Tuli, Jamie Ryu, Dinesh Gehlot, Kapil Porwal, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73272
to look at the new patch set (#4).
Change subject: soc/intel/cmn/tom: Cache TOM region early ......................................................................
soc/intel/cmn/tom: Cache TOM region early
This patch implements a module that can store the top_of_ram (TOM) address into non-volatile space (CMOS) during the first boot and use it across all consecutive boot.
As top_of_ram address is not known until FSP-M has exited, it results into lacking of MTRR programming to cache the 16 MB TOM, hence accessing that range during FSP-M and/or late romstage causing long access times.
Purpose of this driver code is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable).
TEST=Able to build and boot google/rex to ChromeOS.
Without this patch: 950:calling FspMemoryInit 936,811 (19,941) 951:returning from FspMemoryInit 1,041,935 (105,123)
With this patch: 950:calling FspMemoryInit 905,108 (20,103) 951:returning from FspMemoryInit 987,038 (81,929)
Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f Signed-off-by: Subrata Banik subratabanik@google.com --- A src/soc/intel/common/basecode/include/intelbasecode/tom.h A src/soc/intel/common/basecode/tom/Kconfig A src/soc/intel/common/basecode/tom/Makefile.inc A src/soc/intel/common/basecode/tom/tom.c 4 files changed, 184 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/73272/4