Change in coreboot[master]: soc/intel/alderlake: Fix GPP Index as per PCH EDS 630094/645550

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62762 )

Change subject: soc/intel/alderlake: Fix GPP Index as per PCH EDS 630094/645550
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soc/intel/alderlake: Fix GPP Index as per PCH EDS 630094/645550

This patch fixes GPP Index as per ADL-P and ADL-N PCH EDS.

+------------------+------------------+------------------+
|                  |     ADL-P        |      ADL-N       |
+------------------+------------------+------------------+
| GPIO Community 0 | GPP_B/T/A        | GPP_B/T/A        |
| GPIO Community 1 | GPP_S/H/D        | GPP_S/I/H/D      |
| GPIO Community 2 | GPD              | GPD              |
| GPIO Community 4 | GPP_C/F/HVCMOD/E | GPP_C/F/HVCMOD/E |
| GPIO Community 5 | GPP_R/SPI0       | GPP_R/SPI0       |
+------------------+------------------+------------------+

Signed-off-by: Subrata Banik 
Change-Id: I67fd7e0c94bf794b90140d4ebbab4aa15536331f
---
M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
1 file changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/62762/1

diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
index 80e656c..5ec5003 100644
--- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
@@ -11,12 +11,12 @@
  * Refer to Alder Lake PCH EDS Chapter 27, MISCCFG register offset 0x10
  * for each GPIO community to get GPIO group to GPE_DWx assignment.
  */
+/* GPIO COMM 0 */
 #define GPP_B			0x0
 #define GPP_T			INC(GPP_B)
 #define GPP_A			INC(GPP_T)
-#define GPP_R			INC(GPP_A)
-#define GPD			INC(GPP_R)
-#define GPP_S			INC(GPD)
+/* GPIO COMM 1 */
+#define GPP_S			INC(GPP_A)
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 #define GPP_I			INC(GPP_S)
 #define GPP_H			INC(GPP_I)
@@ -24,9 +24,16 @@
 #define GPP_H			INC(GPP_S)
 #endif
 #define GPP_D			INC(GPP_H)
-#define GPP_F			0xA
-#define GPP_C			INC(GPP_F)
-#define GPP_E			INC(GPP_C)
+/* GPIO COMM 2 */
+#define GPD			INC(GPP_D)
+/* GPIO COMM 4 */
+#define GPP_C			INC(GPD)
+#define GPP_F			INC(GPP_C)
+#define GPP_HVMOS		INC(GPP_F)
+#define GPP_E			INC(GPP_HVMOS)
+/* GPIO COMM 5 */
+#define GPP_R			INC(GPP_E)
+#define GPP_SPI0		INC(GPP_R)

#define GPIO_MAX_NUM_PER_GROUP	26