Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20977
Change subject: nb/intel/i440bx: [WIP] Implement CBMEM in romstage ......................................................................
nb/intel/i440bx: [WIP] Implement CBMEM in romstage
An attempt to implement CBMEM in romstage.
Should benefit all 440BX boards but currently only being tested on ASUS P2B-LS.
Currently does not boot and I need your help on the mailing list.
Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Signed-off-by: Keith Hui buurin@gmail.com --- M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/northbridge.c A src/northbridge/intel/i440bx/ram_calc.c 4 files changed, 127 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/20977/1
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 36d4754..45cdd9c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select LATE_CBMEM_INIT select UDELAY_IO
config SDRAMPWR_4DIMM diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index ecefe6a..f900c50 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,8 +17,10 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
ramstage-y += northbridge.c +ramstage-y += ram_calc.c
romstage-y += raminit.c romstage-y += debug.c +romstage-y += ram_calc.c
endif diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index dba7880..414ae99 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,7 +67,7 @@ ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768);
- set_late_cbmem_top(tomk * 1024); + // set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c new file mode 100644 index 0000000..5e00545 --- /dev/null +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2012 ChromeOS Authors + * Copyright (C) 2017 Keith Hui buurin@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <cpu/intel/romstage.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <commonlib/helpers.h> +#include "i440bx.h" + +unsigned long get_top_of_ram(void); + +unsigned long get_top_of_ram(void) +{ + return pci_read_config8(NB, DRB7) * 8 * MiB; +} + +static unsigned long smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + /* + * SMRAM - System Management RAM Control Register + * 0x72 + * [7:4] Not relevant to this function. + * [3:3] Global SMRAM Enable (G_SMRAME) + * [2:0] Hardwired to 010. + + * ESMRAMC - Extended System Management RAM Control + * 0x73 + * [7:7] H_SMRAM_EN + * 1 = When G_SMRAME=1, High SMRAM space is enabled at + * 0x100A0000-0x100FFFFF and forwarded to DRAM address + * 0x000A0000-0x000FFFFF. + * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at + * 0x000A0000-0x000BFFFF. + * [6:3] Not relevant to this function. + * [2:1] TSEG Size (T_SZ) + * Selects the size of the TSEG memory block, if enabled. + * 00 = 128KiB + * 01 = 256KiB + * 10 = 512KiB + * 11 = 1MiB + * [0:0] TSEG_EN + * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to + * appear between DRAM address (TOM-<TSEG Size>) to TOM. + + * Source: 440BX datasheet, pages 3-28 thru 3-29. + */ + unsigned long tom = get_top_of_ram(); + + #if ENV_ROMSTAGE + /* + * In romstage, gtom() above returns 0 if DRB7=0 + * (ie. RAM init isn't done). + * Pass it on. This should not happen in ramstage. + */ + if (tom == 0) + return 0; + #endif + + printk(BIOS_DEBUG, "get_top_of_ram() = %08lx", tom); + + int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; // H_SMRAM_EN and T_SZ + int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; // G_SMRAME + if ((tseg & 0x1) && gsmrame) { + int tseg_size = 128 * KiB * (1 << (tseg >> 1)); + tom -= tseg_size; + } + return tom; +} + +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + return (void *) top_of_ram; +} + +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + uintptr_t tom; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. + */ + tom = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, tom - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, tom - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +}
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Keith Hui (Code Review)