Change in coreboot[master]: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA

[Raul Rangel (Code Review)]

Attention is currently required from: Arthur Heymans, Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59130 )

Change subject: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA
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Patch Set 1:

(1 comment)

File src/soc/amd/common/block/lpc/Kconfig:

https://review.coreboot.org/c/coreboot/+/59130/comment/088cad8d_70c826db 
PS1, Line 24: 
            : config FSP_ALIGNMENT_FSP_S
            : 	int
            : 	default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
            : 
            : config FSP_ALIGNMENT_FSP_M
            : 	int
            : 	default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
> cbfs always has a 64 byte alignment. […]

The metadata does, the actual payload doesn't though.