[XS] Change in coreboot[main]: mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79244?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC
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mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC

In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system
and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level
triggered and it causes AP (Application Processor) to keep sending
GET_NEXT_EVENT to EC during resume from suspend by connecting AC.

So we change GPP_F17 to edge triggered to avoid this condition.

BUG=b:308716748
TEST=Original failure rate was 7 out of 10 times and it reduced to
0 out of 60 times on six joxer systems.

Signed-off-by: Scott Chao 
Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
Reviewed-by: Reka Norman 
Reviewed-by: Paul Menzel 
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, but someone else must approve
  Paul Menzel: Looks good to me, but someone else must approve
  Reka Norman: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 781f00a..5d83e7a 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -242,7 +242,7 @@
    /* F16 : NC */
    PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
    /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
-	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
    PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
    /* F19 : Not available */