Change in coreboot[master]: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding

[Michał Żygowski (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63461 )

Change subject: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
......................................................................

soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding

Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.

Signed-off-by: Michał Żygowski 
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
---
M src/soc/intel/alderlake/bootblock/pch.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/63461/1

diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index 60f3a85..bd204cd 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -103,8 +103,8 @@

void pch_early_iorange_init(void)
 {
-	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F |
+			      LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;

/* IO Decode Range */
    if (CONFIG(DRIVERS_UART_8250IO))