Change in coreboot[master]: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela.
Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Bernardo Perez Priego, Ronak Kanabar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52783

to look at the new patch set (#6).

Change subject: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
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soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO

Adding GPIO definition for community 3 which is CPU reserved GPIO used
by CPU side PCIe root ports. We did not have this definition since
FSP used to program this GPIOs. Now, instead of FSP, coreboot programs
CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode.
Thus adding definition of this virtual GPIOs in this CL.

BUG=None
BRANCH=None
TEST=Check if correct registers are being programmed

Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/alderlake/gpio.c
M src/soc/intel/alderlake/include/soc/gpio_defs.h
M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
3 files changed, 237 insertions(+), 100 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/52783/6