[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list

[Eran Mitrani (Code Review)]

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70163 )

Change subject: soc/intel/alderlake: skip external buses for D-states list
......................................................................

soc/intel/alderlake: skip external buses for D-states list

The devices in the list that was introduced in commit
c66ea98577681f6eded53ca56a7ba945d2a18e31
("soc/intel/alderlake: provide a list of D-states to enter LPM")
are all internal. This CL skips the external buses. (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)

BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani 
---
M src/soc/intel/alderlake/acpi.c
1 file changed, 23 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/70163/1

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index c874067..837099e 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -21,13 +21,11 @@
 #include <cpu/cpu.h>
 #include <types.h>

-
 #define DEFAULT_CPU_D_STATE	D0
 #define LPI_STATES_ALL		0xff
 #define LPI_REVISION		0
 #define LPI_ENABLED		1

-
 /*
  * List of supported C-states in this processor.
  */
@@ -251,6 +249,9 @@
    	return DEFAULT_CPU_D_STATE;

case DEVICE_PATH_PCI:
+		/* skip external buses*/
+		if (dev->bus->secondary != 0)
+			return NONE;
    	for (size_t i = 0; i < ARRAY_SIZE(min_pci_sleep_states); i++)
    		if (min_pci_sleep_states[i].pci_dev == dev->path.pci.devfn)
    			return min_pci_sleep_states[i].min_sleep_state;