Andre Heider has uploaded this change for review. ( https://review.coreboot.org/23783
Change subject: soc/nvidia/tegra210: add missing bl31 params ......................................................................
soc/nvidia/tegra210: add missing bl31 params
The ATF tegra210 platform supports more than the currently used 'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h in the ATF tree.
Add the missing parameters and set them accordingly.
Successfully tested with with UARTB.
Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Signed-off-by: Andre Heider a.heider@gmail.com --- M src/soc/nvidia/tegra210/arm_tf.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23783/1
diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 28966c8..2d278ed 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -22,7 +22,12 @@ #include <symbols.h>
typedef struct bl31_plat_params { - uint32_t tzdram_size; + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } bl31_plat_params_t;
static bl31_plat_params_t t210_plat_params; @@ -36,6 +41,8 @@
assert(tz_size_mib < 4096); t210_plat_params.tzdram_size = tz_size_mib * MiB; + t210_plat_params.tzdram_base = tz_base_mib * MiB; + t210_plat_params.uart_id = 1;
dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params));